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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rxtx_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
rxtx_lint
 
 
 
 

 
 
       
 
 
              
              Dut
              
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="rxtx_dut.params"/>
              
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 
 
 
 

 
 
 
 
  
 
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/uart_rxtx_lint
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`rxtx_lint`
41	131	jt_eaton
42
43
44	133	jt_eaton
45	135	jt_eaton
46	131	jt_eaton
47
48	135	jt_eaton
49	131	jt_eaton
50
51	135	jt_eaton
52			`Dut`
53
54
55			`ipxact:library="logic"`
56			`ipxact:name="uart"`
57			`ipxact:version="rxtx_dut.params"/>`
58
59
60	131	jt_eaton
61
62
63	135	jt_eaton
64			`lint`
65			`:Lint:`
66			`Verilog`
67			`fs-lint`
68
69	131	jt_eaton
70
71
72	135	jt_eaton
73			`rtl_check`
74
75
76			`ipxact:library="Testbench"`
77			`ipxact:name="toolflow"`
78			`ipxact:version="rtl_check"/>`
79
80
81	131	jt_eaton
82	135	jt_eaton
83	131	jt_eaton
84
85
86
87
88	135	jt_eaton
89	131	jt_eaton
90
91
92
93	135	jt_eaton
94	131	jt_eaton
95
96
97
98	135	jt_eaton
99			`fs-lint`
100	131	jt_eaton
101	135	jt_eaton
102
103			`../verilog/lint/uart_rxtx_lint`
104			`verilogSourcemodule`
105
106	131	jt_eaton
107
108	135	jt_eaton
109	131	jt_eaton
110
111
112
113	135	jt_eaton
114	131	jt_eaton
115
116
117
118	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_rxtx_lint.xml] - Blame information for rev 135