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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_duth.design.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
opencores.org
logic
uart
tx_duth.design

 

clk



 

cts_out



 

cts_pad_in



 

divider_in



 

parity_enable



 

reset



 

rts_in



 

rts_pad_out



 

rxd_data_avail



 

rxd_data_avail_stb



 

rxd_data_out



 

rxd_force_parity



 

rxd_pad_in



 

rxd_parity



 

rxd_parity_error



 

rxd_stop_error



 

txd_break



 

txd_buffer_empty



 
 
 

txd_data_in



 

txd_force_parity



 

txd_load



 

txd_pad_out



 

txd_parity



 
 


 

dut


 DIV
 DIV_SIZE
 PRESCALE
 PRE_SIZE
 SIZE
 TX_FIFO_SIZE
 TX_FIFO_WORDS





Line No.	Rev	Author	Line
1	133	jt_eaton
2
9	135	jt_eaton
10			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
11	133	jt_eaton	`xmlns:socgen="http://opencores.org"`
12			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
13	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
14			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
15			`opencores.org`
16			`logic`
17			`uart`
18			`tx_duth.design`
19
20	133	jt_eaton
21	135	jt_eaton
22			`clk`
23
24
25
26	133	jt_eaton
27	135	jt_eaton
28			`cts_out`
29
30
31
32	133	jt_eaton
33	135	jt_eaton
34			`cts_pad_in`
35
36
37
38	133	jt_eaton
39	135	jt_eaton
40			`divider_in`
41
42
43
44	133	jt_eaton
45	135	jt_eaton
46			`parity_enable`
47
48
49
50	133	jt_eaton
51	135	jt_eaton
52			`reset`
53
54
55
56	133	jt_eaton
57	135	jt_eaton
58			`rts_in`
59
60
61
62	133	jt_eaton
63	135	jt_eaton
64			`rts_pad_out`
65
66
67
68	133	jt_eaton
69	135	jt_eaton
70			`rxd_data_avail`
71
72
73
74	133	jt_eaton
75	135	jt_eaton
76			`rxd_data_avail_stb`
77
78
79
80	133	jt_eaton
81	135	jt_eaton
82			`rxd_data_out`
83
84
85
86	133	jt_eaton
87	135	jt_eaton
88			`rxd_force_parity`
89
90
91
92	133	jt_eaton
93	135	jt_eaton
94			`rxd_pad_in`
95
96
97
98	133	jt_eaton
99	135	jt_eaton
100			`rxd_parity`
101
102
103
104	133	jt_eaton
105	135	jt_eaton
106			`rxd_parity_error`
107
108
109
110	133	jt_eaton
111	135	jt_eaton
112			`rxd_stop_error`
113
114
115
116	133	jt_eaton
117	135	jt_eaton
118			`txd_break`
119
120
121
122	133	jt_eaton
123	135	jt_eaton
124			`txd_buffer_empty`
125
126
127
128	133	jt_eaton
129
130
131	135	jt_eaton
132			`txd_data_in`
133
134
135
136	133	jt_eaton
137	135	jt_eaton
138			`txd_force_parity`
139
140
141
142	133	jt_eaton
143	135	jt_eaton
144			`txd_load`
145
146
147
148	133	jt_eaton
149	135	jt_eaton
150			`txd_pad_out`
151
152
153
154	133	jt_eaton
155	135	jt_eaton
156			`txd_parity`
157
158
159
160	133	jt_eaton
161
162	135	jt_eaton
163
164
165
166			`dut`
167
168
169			`DIV`
170			`DIV_SIZE`
171			`PRESCALE`
172			`PRE_SIZE`
173			`SIZE`
174			`TX_FIFO_SIZE`
175			`TX_FIFO_WORDS`
176
177
178
179

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_duth.design.xml] - Blame information for rev 135