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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_lint.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
uart
tx_lint
 
 
 

 
 
       
 
 
 
              
              Dut
              
              
                                   ipxact:library="logic"
                                   ipxact:name="uart"
                                   ipxact:version="tx_dut.params"/>
              
 
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
 
              
              rtl_check
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="rtl_check"/>
              
              
 
      
 
 
 
 
 
 
 

 
 
 
 
 
  
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/uart_tx_lint
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`uart`
40			`tx_lint`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47	135	jt_eaton
48	131	jt_eaton
49
50
51	135	jt_eaton
52			`Dut`
53
54
55			`ipxact:library="logic"`
56			`ipxact:name="uart"`
57			`ipxact:version="tx_dut.params"/>`
58
59	131	jt_eaton
60	135	jt_eaton
61	131	jt_eaton
62
63
64	135	jt_eaton
65			`lint`
66			`:Lint:`
67			`Verilog`
68			`fs-lint`
69
70	131	jt_eaton
71
72
73	135	jt_eaton
74			`rtl_check`
75
76
77			`ipxact:library="Testbench"`
78			`ipxact:name="toolflow"`
79			`ipxact:version="rtl_check"/>`
80
81
82	131	jt_eaton
83	135	jt_eaton
84	131	jt_eaton
85
86
87
88
89
90
91	135	jt_eaton
92	131	jt_eaton
93
94
95
96
97	135	jt_eaton
98	131	jt_eaton
99
100
101	135	jt_eaton
102			`fs-lint`
103	131	jt_eaton
104	135	jt_eaton
105
106			`../verilog/lint/uart_tx_lint`
107			`verilogSourcemodule`
108
109	131	jt_eaton
110	135	jt_eaton
111	131	jt_eaton
112
113
114
115	135	jt_eaton
116	131	jt_eaton
117
118
119
120
121
122	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_lint.xml] - Blame information for rev 135