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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
usb_epp
def
 
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
          
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
          
      
 
  
 
 
 

 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      usb_epp_def
    
  

 
 
 

 
 
 

       
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

 
 
clk
wire
in

 
reset
wire
in

 
 
 
eppastb_in
wire
in

 
eppdstb_in
wire
in

 
usbflag_in
wire
in

 
eppwait_out
wire
out

 
eppwait_in
wire
in

 
eppwait_oe
wire
out

 
usbwr_out
wire
out

 
usbwr_oe
wire
out

 
usbwr_in
wire
in

 
usbmode_out
wire
out

 
usbmode_oe
wire
out

 
usbmode_in
wire
in

 
usboe_out
wire
out

 
usboe_oe
wire
out

 
usboe_in
wire
in

 
usbadr_out
wire
out
10

 
usbadr_oe
wire
out

 
usbadr_in
wire
in
10

 
usbpktend_out
wire
out

 
usbpktend_oe
wire
out

 
usbpktend_in
wire
in

 
usbdir_out
wire
out

 
usbdir_oe
wire
out

 
usbdir_in
wire
in

 
eppdb_in
wire
in
70

 
eppdb_out
wire
out
70

 
eppdb_oe
wire
out

 
eppwr_in
wire
in

 
usbclk_out
wire
out

 
usbclk_oe
wire
out

 
usbclk_in
wire
in

 
usbrdy_in
wire
in

 

 
 

 
 
 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/usb_epp_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/usb_epp_def
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`usb_epp`
40			`def`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46	135	jt_eaton	`slave_clk`
47
48
49
50
51
52
53			`clk`
54			`clk`
55
56
57
58
59
60
61	131	jt_eaton
62
63	135	jt_eaton	`slave_reset`
64
65
66
67
68
69
70			`reset`
71			`reset`
72
73
74
75
76	131	jt_eaton
77	135	jt_eaton
78	131	jt_eaton
79	135	jt_eaton
80	131	jt_eaton
81	135	jt_eaton
82	131	jt_eaton
83
84	135	jt_eaton
85	131	jt_eaton
86	135	jt_eaton
87			`gen_verilog`
88			`104.0`
89			`none`
90			`:common:`
91			`tools/verilog/gen_verilog`
92
93
94			`destination`
95			`usb_epp_def`
96
97
98
99	131	jt_eaton
100
101
102	135	jt_eaton
103	131	jt_eaton
104
105
106	135	jt_eaton
107
108	131	jt_eaton
109	135	jt_eaton
110			`verilog`
111
112
113			`ipxact:library="Testbench"`
114			`ipxact:name="toolflow"`
115			`ipxact:version="verilog"/>`
116
117
118	131	jt_eaton
119
120
121	135	jt_eaton
122
123
124			`common:common:`
125	131	jt_eaton
126	135	jt_eaton	`Verilog`
127
128
129			`fs-common`
130
131
132	131	jt_eaton
133
134
135	135	jt_eaton
136			`sim:Simulation:`
137	131	jt_eaton
138	135	jt_eaton	`Verilog`
139
140
141			`fs-sim`
142
143
144	131	jt_eaton
145	135	jt_eaton
146			`syn:Synthesis:`
147	131	jt_eaton
148	135	jt_eaton	`Verilog`
149
150
151			`fs-syn`
152
153
154	131	jt_eaton
155
156	135	jt_eaton
157			`doc`
158
159
160			`ipxact:library="Testbench"`
161			`ipxact:name="toolflow"`
162			`ipxact:version="documentation"/>`
163
164			`:Documentation:`
165			`Verilog`
166
167	131	jt_eaton
168
169	135	jt_eaton
170	131	jt_eaton
171
172
173	135	jt_eaton
174	131	jt_eaton
175
176	135	jt_eaton	`clk`
177			`wire`
178			`in`
179
180	131	jt_eaton
181	135	jt_eaton	`reset`
182			`wire`
183			`in`
184
185	131	jt_eaton
186
187
188	135	jt_eaton	`eppastb_in`
189			`wire`
190			`in`
191
192	131	jt_eaton
193	135	jt_eaton	`eppdstb_in`
194			`wire`
195			`in`
196
197	131	jt_eaton
198	135	jt_eaton	`usbflag_in`
199			`wire`
200			`in`
201
202	131	jt_eaton
203	135	jt_eaton	`eppwait_out`
204			`wire`
205			`out`
206
207	131	jt_eaton
208	135	jt_eaton	`eppwait_in`
209			`wire`
210			`in`
211
212	131	jt_eaton
213	135	jt_eaton	`eppwait_oe`
214			`wire`
215			`out`
216
217	131	jt_eaton
218	135	jt_eaton	`usbwr_out`
219			`wire`
220			`out`
221
222	131	jt_eaton
223	135	jt_eaton	`usbwr_oe`
224			`wire`
225			`out`
226
227	131	jt_eaton
228	135	jt_eaton	`usbwr_in`
229			`wire`
230			`in`
231
232	131	jt_eaton
233	135	jt_eaton	`usbmode_out`
234			`wire`
235			`out`
236
237	131	jt_eaton
238	135	jt_eaton	`usbmode_oe`
239			`wire`
240			`out`
241
242	131	jt_eaton
243	135	jt_eaton	`usbmode_in`
244			`wire`
245			`in`
246
247	131	jt_eaton
248	135	jt_eaton	`usboe_out`
249			`wire`
250			`out`
251
252	131	jt_eaton
253	135	jt_eaton	`usboe_oe`
254			`wire`
255			`out`
256
257	131	jt_eaton
258	135	jt_eaton	`usboe_in`
259			`wire`
260			`in`
261
262	131	jt_eaton
263	135	jt_eaton	`usbadr_out`
264			`wire`
265			`out`
266			`10`
267
268	131	jt_eaton
269	135	jt_eaton	`usbadr_oe`
270			`wire`
271			`out`
272
273	131	jt_eaton
274	135	jt_eaton	`usbadr_in`
275			`wire`
276			`in`
277			`10`
278
279	131	jt_eaton
280	135	jt_eaton	`usbpktend_out`
281			`wire`
282			`out`
283
284	131	jt_eaton
285	135	jt_eaton	`usbpktend_oe`
286			`wire`
287			`out`
288
289	131	jt_eaton
290	135	jt_eaton	`usbpktend_in`
291			`wire`
292			`in`
293
294	131	jt_eaton
295	135	jt_eaton	`usbdir_out`
296			`wire`
297			`out`
298
299	131	jt_eaton
300	135	jt_eaton	`usbdir_oe`
301			`wire`
302			`out`
303
304	131	jt_eaton
305	135	jt_eaton	`usbdir_in`
306			`wire`
307			`in`
308
309	131	jt_eaton
310	135	jt_eaton	`eppdb_in`
311			`wire`
312			`in`
313			`70`
314
315	131	jt_eaton
316	135	jt_eaton	`eppdb_out`
317			`wire`
318			`out`
319			`70`
320
321	131	jt_eaton
322	135	jt_eaton	`eppdb_oe`
323			`wire`
324			`out`
325
326	131	jt_eaton
327	135	jt_eaton	`eppwr_in`
328			`wire`
329			`in`
330
331	131	jt_eaton
332	135	jt_eaton	`usbclk_out`
333			`wire`
334			`out`
335
336	131	jt_eaton
337	135	jt_eaton	`usbclk_oe`
338			`wire`
339			`out`
340
341	131	jt_eaton
342	135	jt_eaton	`usbclk_in`
343			`wire`
344			`in`
345
346	131	jt_eaton
347	135	jt_eaton	`usbrdy_in`
348			`wire`
349			`in`
350
351	131	jt_eaton
352	135	jt_eaton
353	131	jt_eaton
354
355	135	jt_eaton
356	131	jt_eaton
357
358
359	134	jt_eaton
360
361
362	135	jt_eaton
363	134	jt_eaton
364	135	jt_eaton
365			`fs-common`
366	134	jt_eaton
367	135	jt_eaton
368
369			`../verilog/top.body`
370			`verilogSourcefragment`
371
372	134	jt_eaton
373
374	135	jt_eaton
375	134	jt_eaton
376
377
378
379
380	135	jt_eaton
381			`fs-sim`
382	134	jt_eaton
383	135	jt_eaton
384
385			`../verilog/copyright`
386			`verilogSourceinclude`
387
388	134	jt_eaton
389	135	jt_eaton
390
391			`../verilog/common/usb_epp_def`
392			`verilogSourcemodule`
393
394	134	jt_eaton
395
396
397	135	jt_eaton
398			`dest_dir`
399			`../views/sim/`
400			`verilogSourcelibraryDir`
401
402	134	jt_eaton
403
404
405	135	jt_eaton
406	134	jt_eaton
407
408
409
410
411	135	jt_eaton
412			`fs-syn`
413	134	jt_eaton
414	135	jt_eaton
415
416			`../verilog/copyright`
417			`verilogSourceinclude`
418
419	134	jt_eaton
420	135	jt_eaton
421
422			`../verilog/common/usb_epp_def`
423			`verilogSourcemodule`
424
425	134	jt_eaton
426
427
428	135	jt_eaton
429			`dest_dir`
430			`../views/syn/`
431			`verilogSourcelibraryDir`
432
433	134	jt_eaton
434
435	135	jt_eaton
436	134	jt_eaton
437
438
439
440
441	135	jt_eaton
442	134	jt_eaton
443
444	135	jt_eaton
445
446
447
448

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [usb_epp/] [rtl/] [xml/] [usb_epp_def.xml] - Blame information for rev 135