Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

logic

vga_char_ctrl

def

 slave_clk

        clk

        clk

 slave_reset

        reset

        reset

 vga

        hsync_n_pad_out

        hsync_n_pad_out

        vsync_n_pad_out

        vsync_n_pad_out

        red_pad_out

        red_pad_out

          20

        green_pad_out

        green_pad_out

          20

        blue_pad_out

        blue_pad_out

          10

  gen_verilog

  104.0

  none

  :*common:*

  tools/verilog/gen_verilog

      destination

      vga_char_ctrl_def

      fs-common

        ../verilog/top.body

        verilogSourcefragment

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/common/vga_char_ctrl_def

        verilogSourcemodule

        char_display

        ../verilog/char_display

        verilogSourcemodule

        char_gen

        ../verilog/char_gen

        verilogSourcemodule

        svga_timing_generation

        ../verilog/svga_timing_generation

        verilogSourcemodule

        video_out

        ../verilog/video_out

        verilogSourcemodule

        dest_dir

        ../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/common/vga_char_ctrl_def

        verilogSourcemodule

        char_display

        ../verilog/char_display

        verilogSourcemodule

        char_gen

        ../verilog/char_gen

        verilogSourcemodule

        svga_timing_generation

        ../verilog/svga_timing_generation

        verilogSourcemodule

        video_out

        ../verilog/video_out

        verilogSourcemodule

        dest_dir

        ../views/syn/

        verilogSourcelibraryDir

                                Hierarchical

              Hierarchical

                      Hierarchical

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              common:*common:*

              Verilog

                            fs-common

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

clk

  wire

in

reset

  wire

in

hsync_n_pad_out

  wire

out

vsync_n_pad_out

  wire

out

red_pad_out

  wire

out

green_pad_out

  wire

out

blue_pad_out

  wire

out

ascii_load

  wire

in

add_l_load

wire

in

add_h_load

wire

in

wdata

wire

in

70

address

reg

out

130

char_color

wire

in

70

back_color

wire

in

70

cursor_color

wire

in

70