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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [sim/] [testbenches/] [xml/] [vga_char_ctrl_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
logic
vga_char_ctrl
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      vga_char_ctrl_def_tb
    
  

 
 
 

 
 
 
 
 
 
 

 
 
 
       
 
              
              Params
              
              
                                   ipxact:library="logic"
                                   ipxact:name="vga_char_ctrl"
                                   ipxact:version="def_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   ipxact:library="logic"
                                   ipxact:name="vga_char_ctrl"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/sram.load
        verilogSourcefragment
      
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/vga_char_ctrl_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/vga_char_ctrl_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`logic`
39			`vga_char_ctrl`
40			`def_tb`
41	131	jt_eaton
42
43
44
45
46
47	135	jt_eaton
48	131	jt_eaton
49
50
51	135	jt_eaton
52			`gen_verilog`
53			`104.0`
54			`none`
55			`:common:`
56			`tools/verilog/gen_verilog`
57
58
59			`destination`
60			`vga_char_ctrl_def_tb`
61
62
63
64	131	jt_eaton
65
66
67	135	jt_eaton
68	131	jt_eaton
69
70
71
72
73
74
75	135	jt_eaton
76	131	jt_eaton
77
78
79	135	jt_eaton
80	131	jt_eaton
81	135	jt_eaton
82			`Params`
83
84
85			`ipxact:library="logic"`
86			`ipxact:name="vga_char_ctrl"`
87			`ipxact:version="def_dut.params"/>`
88
89
90	131	jt_eaton
91
92	135	jt_eaton
93			`Bfm`
94
95			`ipxact:library="logic"`
96			`ipxact:name="vga_char_ctrl"`
97			`ipxact:version="bfm.design"/>`
98
99	131	jt_eaton
100
101
102	135	jt_eaton
103			`icarus`
104
105
106			`ipxact:library="Testbench"`
107			`ipxact:name="toolflow"`
108			`ipxact:version="icarus"/>`
109
110
111	131	jt_eaton
112
113
114
115
116	135	jt_eaton
117			`common:common:`
118			`Verilog`
119
120
121			`fs-common`
122
123
124	131	jt_eaton
125
126	135	jt_eaton
127			`sim:Simulation:`
128			`Verilog`
129
130
131			`fs-sim`
132
133
134	131	jt_eaton
135
136
137	135	jt_eaton
138			`lint:Lint:`
139			`Verilog`
140
141
142			`fs-lint`
143
144
145	131	jt_eaton
146	135	jt_eaton
147	131	jt_eaton
148
149
150
151	135	jt_eaton
152	131	jt_eaton
153	135	jt_eaton
154	131	jt_eaton
155	135	jt_eaton
156			`fs-common`
157	131	jt_eaton
158	135	jt_eaton
159
160			`../verilog/sram.load`
161			`verilogSourcefragment`
162
163	131	jt_eaton
164
165	135	jt_eaton
166
167			`../verilog/tb.ext`
168			`verilogSourcefragment`
169
170	131	jt_eaton
171
172
173	135	jt_eaton
174	131	jt_eaton
175
176
177	135	jt_eaton
178			`fs-sim`
179	131	jt_eaton
180	135	jt_eaton
181
182			`../verilog/common/vga_char_ctrl_def_tb`
183			`verilogSourcemodule`
184
185	131	jt_eaton
186
187
188	135	jt_eaton
189	131	jt_eaton
190
191
192	135	jt_eaton
193			`fs-lint`
194	131	jt_eaton
195	135	jt_eaton
196
197			`../verilog/common/vga_char_ctrl_def_tb`
198			`verilogSourcemodule`
199
200	131	jt_eaton
201
202
203	135	jt_eaton
204	131	jt_eaton
205
206
207
208
209
210	135	jt_eaton
211	131	jt_eaton
212
213
214
215	135	jt_eaton

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [sim/] [testbenches/] [xml/] [vga_char_ctrl_def_tb.xml] - Blame information for rev 135