Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

wishbone

wb

b.2_rtl

      clk

      The clock input coordinates all activities for the internal logic within the WISHBONE interconnect. All WISHBONE output signals are registered at the rising edge of clk. All WISHBONE input signals are stable before the rising edge of clk.

          true

          CLOCK

          required

          1

          out

          RESET

          optional

          1

          out

          required

          1

          in

          required

          1

          in

        true

      enable

      The enable input determines if a clk cycle should be acted upon or ignored for all operations including reset.

          CLOCK

          illegal

          ENABLE

          required

          1

          out

          optional

          1

          in

          optional

          1

          in

      rst

      The rst input forces the WISHBONE interface to restart. Furthermore, all internal self-starting state machines will be forced into an initial state. This signal only resets the WISHBONE interface. It is not required to reset other parts of an IP core (although it may be used that way).

          true

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          required

          1

          out

          required

          1

          in

          required

          1

          in

        true

      adr

      The adr output array is used to pass a binary address. The higher array boundary is specific to the address width of the core, and the lower array boundary is determined by the data port size and granularity. For example the array size on a 32-bit data port with BYTE granularity is adr[n:2]. In some cases (such as FIFO interfaces) the array may not be present on the interface.

          true

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          out

          required

          in

      cyc

      The cycle output when asserted, indicates that a valid bus cycle is in progress. The signal is asserted for the duration of all bus cycles. For example, during a BLOCK transfer cycle there can be multiple data transfers. The signal is asserted during the first data transfer, and remains asserted until the last data transfer. The signal is useful for interfaces with multi-port interfaces (such as dual port memories). In these cases, the  signal requests use of a common bus from an arbiter.

          true

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          out

          required

          in

      wdata

      The data output array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. wdata[63:0].Also see the rdata[] and sel[] signal descriptions.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          out

          required

          in

      rdata

      The data input array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. rdata[63:0]. Also see the wdata[] and sel[] signal descriptions.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          in

          required

          out

      ack

      The acknowledge input  when asserted, indicates the normal termination of a bus cycle. Also see the err and rty signal descriptions.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          in

          required

          out

      err

      The error input indicates an abnormal cycle termination. The source of the error, and the response generated by the MASTER is defined by the IP core supplier. Also see the ack and rty signal descriptions.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          in

          required

          out

      rty

      The retry input indicates that the interface is not ready to accept or send data, and that the cycle should be retried. When and how the cycle is retried is defined by the IP core supplier. Also see the ack and err signal descriptions.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          in

          required

          out

      sel

      The select output array indicates where valid data is expected on the rdata signal array during READ cycles, and where it is placed on the wdata signal array during WRITE cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit granularity is used on a 64-bit port, then there would be an array of eight select signals with boundaries of sel[7:0]. Each individual select signal correlates to one of eight active bytes on the 64-bit data port. For more information about sel, please refer to the data organization section in Chapter 3 of this specification. Also see the rdata[], wdata[] and stb signal descriptions.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          out

          required

          in

      stb

      The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface such as sel[]. The SLAVE asserts either the ack, err  or rty signals in response to every assertion of the stb signal.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          out

          required

          in

      tagn_i

      The tag input(s)  are user defined, and are used with either MASTER or SLAVE interfaces. ‘N’ in this signal name refers to a tag number because multiple tags may be used (e.g. TAG_I[3]). Tag inputs are used whenever an IP core needs specific information from the interconnection. For example, a MASTER can be designed to monitor the state of a FIFO.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          in

          required

          out

      tagn_o

      The tag output(s) are user defined, and are used with either MASTER or SLAVE interfaces. For example, the tag output(s) can be used to indicate the type of data transfer in progress. Furthermore, ‘N’ in this signal name refers to a tag number because multiple tags may be used. For example, tagn_o[1] may indicate a valid data transfer cycle, tagn_o[2] may indicate an interrupt acknowledge cycle and so on. The exact meaning of each tag is defined by the IP core provider in the WISHBONE DATASHEET.

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          out

          required

          in

      we

      The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.

          true

          CLOCK

          illegal

          ENABLE

          illegal

          RESET

          illegal

          required

          out

          required

          in