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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [sch/] [wb_uart16550_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 2900 300 1 0 0 in_port_vector.sym
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{
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T 2900 300 5 10 1 1 0 6 1 1
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refdes=wb_dat_i[WB_DATA_WIDTH-1:0]
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}
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C 2900 700 1 0 0 in_port_vector.sym
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{
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T 2900 700 5 10 1 1 0 6 1 1
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refdes=wb_adr_i[WB_ADDR_WIDTH-1:0]
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}
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C 2900 1100 1 0 0 in_port.sym
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{
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T 2900 1100 5 10 1 1 0 6 1 1
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refdes=wb_we_i
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}
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C 2900 1500 1 0 0 in_port.sym
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{
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T 2900 1500 5 10 1 1 0 6 1 1
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refdes=wb_stb_i
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}
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C 2900 1900 1 0 0 in_port.sym
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{
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T 2900 1900 5 10 1 1 0 6 1 1
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refdes=wb_sel_i
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}
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C 2900 2300 1 0 0 in_port.sym
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{
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T 2900 2300 5 10 1 1 0 6 1 1
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refdes=wb_rst_i
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}
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C 2900 2700 1 0 0 in_port.sym
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{
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T 2900 2700 5 10 1 1 0 6 1 1
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refdes=wb_cyc_i
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}
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C 2900 3100 1 0 0 in_port.sym
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{
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T 2900 3100 5 10 1 1 0 6 1 1
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refdes=wb_clk_i
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}
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C 2900 3500 1 0 0 in_port.sym
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{
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T 2900 3500 5 10 1 1 0 6 1 1
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refdes=srx_pad_i
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}
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C 2900 3900 1 0 0 in_port.sym
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{
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T 2900 3900 5 10 1 1 0 6 1 1
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refdes=ri_pad_i
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}
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C 2900 4300 1 0 0 in_port.sym
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{
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T 2900 4300 5 10 1 1 0 6 1 1
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refdes=dsr_pad_i
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}
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C 2900 4700 1 0 0 in_port.sym
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{
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T 2900 4700 5 10 1 1 0 6 1 1
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refdes=dcd_pad_i
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}
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C 2900 5100 1 0 0 in_port.sym
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{
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T 2900 5100 5 10 1 1 0 6 1 1
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refdes=cts_pad_i
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}
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C 6900 300  1 0  0 out_port_vector.sym
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{
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T 7900 300 5  10 1 1 0 0 1 1
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refdes=wb_dat_o[WB_DATA_WIDTH-1:0]
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}
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C 6900 700  1 0 0 out_port.sym
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{
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T 7900 700 5  10 1 1 0 0 1 1
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refdes=wb_ack_o
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}
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C 6900 1100  1 0 0 out_port.sym
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{
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T 7900 1100 5  10 1 1 0 0 1 1
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refdes=stx_pad_o
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}
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C 6900 1500  1 0 0 out_port.sym
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{
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T 7900 1500 5  10 1 1 0 0 1 1
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refdes=rts_pad_o
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}
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C 6900 1900  1 0 0 out_port.sym
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{
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T 7900 1900 5  10 1 1 0 0 1 1
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refdes=int_o
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}
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C 6900 2300  1 0 0 out_port.sym
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{
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T 7900 2300 5  10 1 1 0 0 1 1
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refdes=dtr_pad_o
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}
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C 6900 2700  1 0 0 out_port.sym
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{
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T 7900 2700 5  10 1 1 0 0 1 1
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refdes=baud_o
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}

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