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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [sym/] [wb_memory_def.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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B 300 0  5200 1900 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 2050   5 10 1 1 0 0 1 1
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device=wb_memory_def
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T 400 2250 5 10 1 1 0 0 1 1
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refdes=U?
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T 400 2400    0 10 0 1 0 0 1 1
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vendor=opencores.org
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T 400 2400    0 10 0 1 0 0 1 1
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library=wishbone
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T 400 2400    0 10 0 1 0 0 1 1
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component=wb_memory
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T 400 2400    0 10 0 1 0 0 1 1
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version=def
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P 300 200 0 200 10 1 1
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{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=sel_i[wb_byte_lanes-1:0]
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T 400 200 5 10 0 1 0 1 1 1
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pinseq=1
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}
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P 300 400 0 400 10 1 1
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{
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T 400 400 5 10 1 1 0 1 1 1
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pinnumber=dat_i[wb_data_width-1:0]
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 10 1 1
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{
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T 400 600 5 10 1 1 0 1 1 1
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pinnumber=adr_i[wb_addr_width-1:0]
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T 400 600 5 10 0 1 0 1 1 1
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pinseq=3
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}
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P 300 800 0 800 4 0 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=we_i
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T 400 800 5 10 0 1 0 1 1 1
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pinseq=4
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}
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P 300 1000 0 1000 4 0 1
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{
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T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=stb_i
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T 400 1000 5 10 0 1 0 1 1 1
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pinseq=5
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}
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P 300 1200 0 1200 4 0 1
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{
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T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=rst_i
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T 400 1200 5 10 0 1 0 1 1 1
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pinseq=6
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}
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P 300 1400 0 1400 4 0 1
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{
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T 400 1400 5 10 1 1 0 1 1 1
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pinnumber=cyc_i
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T 400 1400 5 10 0 1 0 1 1 1
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pinseq=7
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}
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P 300 1600 0 1600 4 0 1
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{
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T 400 1600 5 10 1 1 0 1 1 1
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pinnumber=clk_i
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T 400 1600 5 10 0 1 0 1 1 1
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pinseq=8
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}
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P 5500 200 5800 200 10 1 1
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{
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T 5400 200 5  10 1 1 0 7 1 1
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pinnumber=dat_o[wb_data_width-1:0]
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T 5400 200 5  10 0 1 0 7 1 1
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pinseq=9
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}
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P 5500 400 5800 400 4 0 1
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{
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T 5400 400 5  10 1 1 0 7 1 1
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pinnumber=ack_o
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T 5500 400 5  10 0 1 0 7 1 1
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pinseq=10
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}

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