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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_memory
def
 
 
 

 
 
 slave_clk
  
  
      
  
    
      
        clk
        clk_i
      
    
        
      
  
 
 
 
 slave_reset
 
 
      
  
    
      
        reset
        rst_i
      
    
                
      
  
 
 
 
wb
   
  
      
        
     
 
        
         adr
         
         adr_i
           wb_addr_width-10
         
       
 
 
 
        
         wdata
         
         dat_i
           wb_data_width-10
         
       
 
 
        
         rdata
         
         dat_o
           wb_data_width-10
         
       
 
 
        
         sel
         
         sel_i
           wb_byte_lanes-10
         
       
 
 
        
         we
         
         we_i
         
       
 
 
        
         cyc
         
         cyc_i
         
       
 
 
        
         stb
         
         stb_i
         
       
 
 
        
         ack
         
         ack_o
         reg
         
       
 
 
     
 
 
        
      
     
 

 

 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      wb_memory_def
    
  

 
 
 
 
 

 
 
 
 
 
 
 
 

        
                        
                                Hierarchical
                                
                        
                
 
 
       
 
 
 
              
              Hierarchical
 
       Hierarchical
              
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

   wb_addr_width24
   wb_data_width32
   wb_byte_lanes4
   dat_width32
   adr_width14
   mem_size16384
   SRAM_MEM_0_FILE"NONE"
   SRAM_MEM_1_FILE"NONE"
   SRAM_MEM_2_FILE"NONE"
   SRAM_MEM_3_FILE"NONE"
 

 
 
 

 
 
 
 
 
  
 
 
    
      fs-common
 
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/wb_memory_def
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/wb_memory_def
        verilogSourcemodule
      
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
  
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [xml/] [wb_memory_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_memory`
40			`def`
41	131	jt_eaton
42
43
44	135	jt_eaton
45	131	jt_eaton
46
47	135	jt_eaton	`slave_clk`
48
49
50
51
52
53
54			`clk`
55			`clk_i`
56
57
58
59
60
61
62	131	jt_eaton
63
64	135	jt_eaton	`slave_reset`
65
66
67
68
69
70
71			`reset`
72			`rst_i`
73
74
75
76
77
78
79	131	jt_eaton
80
81	135	jt_eaton	`wb`
82
83
84
85
86
87	131	jt_eaton
88	135	jt_eaton
89			`adr`
90
91			`adr_i`
92			`wb_addr_width-10`
93
94
95	131	jt_eaton
96
97
98	135	jt_eaton
99			`wdata`
100
101			`dat_i`
102			`wb_data_width-10`
103
104
105	131	jt_eaton
106
107	135	jt_eaton
108			`rdata`
109
110			`dat_o`
111			`wb_data_width-10`
112
113
114	131	jt_eaton
115
116	135	jt_eaton
117			`sel`
118
119			`sel_i`
120			`wb_byte_lanes-10`
121
122
123	131	jt_eaton
124
125	135	jt_eaton
126			`we`
127
128			`we_i`
129
130
131	131	jt_eaton
132
133	135	jt_eaton
134			`cyc`
135
136			`cyc_i`
137
138
139	131	jt_eaton
140
141	135	jt_eaton
142			`stb`
143
144			`stb_i`
145
146
147	131	jt_eaton
148
149	135	jt_eaton
150			`ack`
151
152			`ack_o`
153			`reg`
154
155
156	131	jt_eaton
157
158	135	jt_eaton
159	131	jt_eaton
160	135	jt_eaton
161
162
163
164	131	jt_eaton
165	135	jt_eaton
166	131	jt_eaton
167	135	jt_eaton
168	131	jt_eaton
169
170
171
172
173
174	135	jt_eaton
175	133	jt_eaton
176
177
178	131	jt_eaton
179	135	jt_eaton
180			`gen_verilog`
181			`104.0`
182			`none`
183			`:common:`
184			`tools/verilog/gen_verilog`
185
186
187			`destination`
188			`wb_memory_def`
189
190
191
192	131	jt_eaton
193
194
195
196
197	135	jt_eaton
198	131	jt_eaton
199
200
201
202
203
204
205
206	135	jt_eaton
207
208
209			`Hierarchical`
210
211
212
213	131	jt_eaton
214	135	jt_eaton
215
216	131	jt_eaton
217	135	jt_eaton
218
219
220			`Hierarchical`
221	131	jt_eaton
222	135	jt_eaton	`Hierarchical`
223
224	131	jt_eaton
225	135	jt_eaton
226			`verilog`
227
228
229			`ipxact:library="Testbench"`
230			`ipxact:name="toolflow"`
231			`ipxact:version="verilog"/>`
232
233
234	131	jt_eaton
235
236
237
238
239
240	135	jt_eaton
241			`common:common:`
242	131	jt_eaton
243	135	jt_eaton	`Verilog`
244
245
246			`fs-common`
247
248
249	131	jt_eaton
250
251	135	jt_eaton
252			`sim:Simulation:`
253	131	jt_eaton
254	135	jt_eaton	`Verilog`
255
256
257			`fs-sim`
258
259
260	131	jt_eaton
261	135	jt_eaton
262			`syn:Synthesis:`
263	131	jt_eaton
264	135	jt_eaton	`Verilog`
265
266
267			`fs-syn`
268
269
270	131	jt_eaton
271
272
273	135	jt_eaton
274			`doc`
275
276
277			`ipxact:library="Testbench"`
278			`ipxact:name="toolflow"`
279			`ipxact:version="documentation"/>`
280
281			`:Documentation:`
282			`Verilog`
283
284	131	jt_eaton
285	135	jt_eaton
286	131	jt_eaton
287
288
289
290	135	jt_eaton
291			`wb_addr_width24`
292			`wb_data_width32`
293			`wb_byte_lanes4`
294			`dat_width32`
295			`adr_width14`
296			`mem_size16384`
297			`SRAM_MEM_0_FILE"NONE"`
298			`SRAM_MEM_1_FILE"NONE"`
299			`SRAM_MEM_2_FILE"NONE"`
300			`SRAM_MEM_3_FILE"NONE"`
301	131	jt_eaton
302	135	jt_eaton
303	131	jt_eaton
304
305
306	135	jt_eaton
307	131	jt_eaton
308
309
310
311
312	135	jt_eaton
313	131	jt_eaton
314
315	135	jt_eaton
316			`fs-common`
317	131	jt_eaton
318
319	135	jt_eaton
320
321			`../verilog/top.body`
322			`verilogSourcefragment`
323
324	134	jt_eaton
325
326	135	jt_eaton
327	134	jt_eaton
328
329	135	jt_eaton
330			`fs-sim`
331	134	jt_eaton
332	135	jt_eaton
333
334			`../verilog/copyright`
335			`verilogSourceinclude`
336
337	134	jt_eaton
338	135	jt_eaton
339
340			`../verilog/common/wb_memory_def`
341			`verilogSourcemodule`
342
343	134	jt_eaton
344
345	135	jt_eaton
346			`dest_dir`
347			`../views/sim/`
348			`verilogSourcelibraryDir`
349
350	134	jt_eaton
351
352
353
354
355
356
357	135	jt_eaton
358	134	jt_eaton
359
360
361	135	jt_eaton
362			`fs-syn`
363	134	jt_eaton
364	135	jt_eaton
365
366			`../verilog/copyright`
367			`verilogSourceinclude`
368
369	134	jt_eaton
370	135	jt_eaton
371
372			`../verilog/common/wb_memory_def`
373			`verilogSourcemodule`
374
375	134	jt_eaton
376
377	135	jt_eaton
378			`dest_dir`
379			`../views/syn/`
380			`verilogSourcelibraryDir`
381
382	134	jt_eaton
383
384
385
386	135	jt_eaton
387	134	jt_eaton
388
389
390
391	135	jt_eaton
392	134	jt_eaton
393
394
395
396
397	135	jt_eaton