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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [componentCfg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
opencores.org
wishbone
wb_uart16550
 
 
2
_
_
_
VARIANT

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 
 

 
/doc
 

 
 
 
 
 
 
    
 
          
            default
            def
            def_tb
            def_lint
            
            PRESCALER_PRESET16'h1234
            WB_ADDR_WIDTH8
            WB_DATA_WIDTH8
           
          
 
          
            bus16
            bus16_lit
            bus16_lit_tb
            bus16_lit_lint
            bus16_big
            bus16_big_tb
            bus16_big_lint
            
            PRESCALER_PRESET16'h1234
            WB_ADDR_WIDTH8
            WB_DATA_WIDTH16
            WB_BYTE_LANES2
           
          
 
          
            bus32
            bus32_lit
            bus32_lit_tb
            bus32_lit_lint
            bus32_big
            bus32_big_tb
            bus32_big_lint
            
            PRESCALER_PRESET16'h1234
            WB_ADDR_WIDTH8
            WB_DATA_WIDTH32
            WB_BYTE_LANES4
           
          
    
 
 

 
wb_uart16550/sim
 
 
 
 
 

 
 

wb_uart16550_def_tb
def_tb

    PERIOD40
    TIMEOUT100000

 
root.dutwb
 

  
  wb_uart16550_def
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 

wb_uart16550_bus16_lit_tb
bus16_lit_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus16_lit
  TB.test.dut
  


  icaruscoverage

 

 
 
 

wb_uart16550_bus16_big_tb
bus16_big_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus16_big
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 

wb_uart16550_bus32_lit_tb
bus32_lit_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus32_lit
  TB.test.dut
  


  icaruscoverage


 
 

wb_uart16550_bus32_big_tb
bus32_big_tb

    PERIOD40
    TIMEOUT100000

root.dutwb

  
  wb_uart16550_bus32_big
  TB.test.dut
  


  icaruscoverage

 

 
 
 
 
 
 

wb_uart16550_def_lint
def_lint

  rtl_check


 
 
 
 

wb_uart16550_bus16_lit_lint
bus16_lit_lint

  rtl_check

 

 
 
 

wb_uart16550_bus16_big_lint
bus16_big_lint

  rtl_check


 
 
 
 

wb_uart16550_bus32_lit_lint
bus32_lit_lint

  rtl_check


 
 

wb_uart16550_bus32_big_lint
bus32_big_lint

  rtl_check


 
 
 

 
 
 
 
 
 
 

 

default
wb_uart16550_def_lint
default

 
 
 
 

bus16_lit_default
wb_uart16550_bus16_lit_lint
default

 
 

bus16_big_default
wb_uart16550_bus16_big_lint
default

 
 
 
 

bus32_lit_default
wb_uart16550_bus32_lit_lint
default

 
 
 

bus32_big_default
wb_uart16550_bus32_big_lint
default

 
 
 

 
 
 
 
 
 
 
 

 

default
wb_uart16550_def_tb
default

 
 
 
 

bus16_lit_default
wb_uart16550_bus16_lit_tb
bus16

 
 

bus16_big_default
wb_uart16550_bus16_big_tb
bus16

 
 
 
 

bus32_lit_default
wb_uart16550_bus32_lit_tb
bus32

 
 
 

bus32_big_default
wb_uart16550_bus32_big_tb
bus32

 
 
 

 
 
 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [componentCfg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6	135	jt_eaton	`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`opencores.org`
11			`wishbone`
12			`wb_uart16550`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20	135	jt_eaton
21
22			`TestBenches`
23			`sim`
24			`testbenches`
25			`testbench`
26			`version`
27
28
29			`Fpgas`
30			`syn`
31			`ise`
32			`chip`
33			`variant`
34
35
36	131	jt_eaton
37
38	135	jt_eaton
39
40	131	jt_eaton
41
42			`/doc`
43
44
45
46
47
48
49
50
51
52
53
54			`default`
55	134	jt_eaton	`def`
56			`def_tb`
57			`def_lint`
58	131	jt_eaton
59			`PRESCALER_PRESET16'h1234`
60	134	jt_eaton	`WB_ADDR_WIDTH8`
61			`WB_DATA_WIDTH8`
62	131	jt_eaton
63
64
65	134	jt_eaton
66			`bus16`
67			`bus16_lit`
68			`bus16_lit_tb`
69			`bus16_lit_lint`
70			`bus16_big`
71			`bus16_big_tb`
72			`bus16_big_lint`
73
74			`PRESCALER_PRESET16'h1234`
75			`WB_ADDR_WIDTH8`
76			`WB_DATA_WIDTH16`
77			`WB_BYTE_LANES2`
78
79
80
81
82			`bus32`
83			`bus32_lit`
84			`bus32_lit_tb`
85			`bus32_lit_lint`
86			`bus32_big`
87			`bus32_big_tb`
88			`bus32_big_lint`
89
90			`PRESCALER_PRESET16'h1234`
91			`WB_ADDR_WIDTH8`
92			`WB_DATA_WIDTH32`
93			`WB_BYTE_LANES4`
94
95
96	131	jt_eaton
97
98
99
100
101			`wb_uart16550/sim`
102
103
104
105
106
107
108
109
110
111			`wb_uart16550_def_tb`
112			`def_tb`
113
114			`PERIOD40`
115			`TIMEOUT100000`
116
117
118			`root.dutwb`
119
120
121
122			`wb_uart16550_def`
123			`TB.test.dut`
124
125
126
127			`icaruscoverage`
128
129
130
131
132
133
134
135
136			`wb_uart16550_bus16_lit_tb`
137			`bus16_lit_tb`
138
139			`PERIOD40`
140			`TIMEOUT100000`
141
142			`root.dutwb`
143
144
145			`wb_uart16550_bus16_lit`
146			`TB.test.dut`
147
148
149
150			`icaruscoverage`
151
152
153
154
155
156
157
158			`wb_uart16550_bus16_big_tb`
159			`bus16_big_tb`
160
161			`PERIOD40`
162			`TIMEOUT100000`
163
164			`root.dutwb`
165
166
167			`wb_uart16550_bus16_big`
168			`TB.test.dut`
169
170
171
172			`icaruscoverage`
173
174
175
176
177
178
179
180
181			`wb_uart16550_bus32_lit_tb`
182			`bus32_lit_tb`
183
184			`PERIOD40`
185			`TIMEOUT100000`
186
187			`root.dutwb`
188
189
190			`wb_uart16550_bus32_lit`
191			`TB.test.dut`
192
193
194
195			`icaruscoverage`
196
197
198
199
200
201			`wb_uart16550_bus32_big_tb`
202			`bus32_big_tb`
203
204			`PERIOD40`
205			`TIMEOUT100000`
206
207			`root.dutwb`
208
209
210			`wb_uart16550_bus32_big`
211			`TB.test.dut`
212
213
214
215			`icaruscoverage`
216
217
218
219
220
221
222
223
224
225
226			`wb_uart16550_def_lint`
227			`def_lint`
228
229			`rtl_check`
230
231
232
233
234
235
236
237			`wb_uart16550_bus16_lit_lint`
238			`bus16_lit_lint`
239
240			`rtl_check`
241
242
243
244
245
246
247
248			`wb_uart16550_bus16_big_lint`
249			`bus16_big_lint`
250
251			`rtl_check`
252
253
254
255
256
257
258
259			`wb_uart16550_bus32_lit_lint`
260			`bus32_lit_lint`
261
262			`rtl_check`
263
264
265
266
267
268			`wb_uart16550_bus32_big_lint`
269			`bus32_big_lint`
270
271			`rtl_check`
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288			`default`
289			`wb_uart16550_def_lint`
290			`default`
291
292
293
294
295
296
297			`bus16_lit_default`
298			`wb_uart16550_bus16_lit_lint`
299			`default`
300
301
302
303
304			`bus16_big_default`
305			`wb_uart16550_bus16_big_lint`
306			`default`
307
308
309
310
311
312
313			`bus32_lit_default`
314			`wb_uart16550_bus32_lit_lint`
315			`default`
316
317
318
319
320
321			`bus32_big_default`
322			`wb_uart16550_bus32_big_lint`
323			`default`
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340			`default`
341			`wb_uart16550_def_tb`
342			`default`
343
344
345
346
347
348
349			`bus16_lit_default`
350			`wb_uart16550_bus16_lit_tb`
351	134	jt_eaton	`bus16`
352	131	jt_eaton
353
354
355
356			`bus16_big_default`
357			`wb_uart16550_bus16_big_tb`
358	134	jt_eaton	`bus16`
359	131	jt_eaton
360
361
362
363
364
365			`bus32_lit_default`
366			`wb_uart16550_bus32_lit_tb`
367	134	jt_eaton	`bus32`
368	131	jt_eaton
369
370
371
372
373			`bus32_big_default`
374			`wb_uart16550_bus32_big_tb`
375	134	jt_eaton	`bus32`
376	131	jt_eaton
377
378
379
380
381
382
383
384
385
386
387
388