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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_lit_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_lit_tb
 
 
 
 
 
 
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      wb_uart16550_bus16_lit_tb
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
       
 
              
              Params
              
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bus16_lit_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
              Verilog
              
              
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
 
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 
 

 
 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
    
      fs-sim
 
 
 
      
        
        ../verilog/common/wb_uart16550_bus16_lit_tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/wb_uart16550_bus16_lit_tb
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_lit_tb`
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49	131	jt_eaton
50
51	135	jt_eaton
52			`gen_verilog`
53			`104.0`
54			`none`
55			`:common:`
56			`tools/verilog/gen_verilog`
57
58
59			`destination`
60			`wb_uart16550_bus16_lit_tb`
61
62
63
64	131	jt_eaton
65
66
67	135	jt_eaton
68	131	jt_eaton
69
70
71	135	jt_eaton
72
73			`UART_MODEL_CLKCNT4'b1100`
74			`UART_MODEL_SIZE4`
75
76	131	jt_eaton
77
78	135	jt_eaton
79	131	jt_eaton
80	135	jt_eaton
81			`Params`
82
83
84			`ipxact:library="wishbone"`
85			`ipxact:name="wb_uart16550"`
86			`ipxact:version="bus16_lit_dut.params"/>`
87
88
89	131	jt_eaton
90
91	135	jt_eaton
92			`Bfm`
93
94			`ipxact:library="wishbone"`
95			`ipxact:name="wb_uart16550"`
96			`ipxact:version="bfm.design"/>`
97
98	131	jt_eaton
99
100
101	135	jt_eaton
102			`icarus`
103
104
105			`ipxact:library="Testbench"`
106			`ipxact:name="toolflow"`
107			`ipxact:version="icarus"/>`
108
109
110	131	jt_eaton
111
112
113
114	135	jt_eaton
115			`headersheaders`
116			`Verilog`
117
118
119	131	jt_eaton
120	135	jt_eaton
121			`common:common:`
122			`Verilog`
123
124
125			`fs-common`
126
127	131	jt_eaton
128	135	jt_eaton
129	131	jt_eaton
130
131	135	jt_eaton
132			`sim:Simulation:`
133			`Verilog`
134
135
136			`fs-sim`
137
138
139	131	jt_eaton
140	135	jt_eaton
141			`lint:Lint:`
142			`Verilog`
143
144
145			`fs-lint`
146
147
148	131	jt_eaton
149
150	135	jt_eaton
151	131	jt_eaton
152
153
154
155
156
157
158	135	jt_eaton
159	131	jt_eaton
160
161
162
163	135	jt_eaton
164	131	jt_eaton
165
166	135	jt_eaton
167			`fs-common`
168	131	jt_eaton
169	135	jt_eaton
170
171			`../verilog/tb.ext`
172			`verilogSourcefragment`
173
174	131	jt_eaton
175	135	jt_eaton
176	131	jt_eaton
177
178
179
180
181	135	jt_eaton
182			`fs-sim`
183	131	jt_eaton
184
185
186	135	jt_eaton
187
188			`../verilog/common/wb_uart16550_bus16_lit_tb`
189			`verilogSourcemodule`
190
191	131	jt_eaton
192
193
194
195
196
197	135	jt_eaton
198	131	jt_eaton
199
200	135	jt_eaton
201			`fs-lint`
202	131	jt_eaton
203	135	jt_eaton
204
205			`../verilog/common/wb_uart16550_bus16_lit_tb`
206			`verilogSourcemodule`
207
208	131	jt_eaton
209
210
211
212
213	135	jt_eaton
214	131	jt_eaton
215
216
217
218	135	jt_eaton
219	131	jt_eaton
220
221
222
223	135	jt_eaton

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_lit_tb.xml] - Blame information for rev 135