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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_big_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_big_tb
 
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
   
    
      destination
      wb_uart16550_bus32_big_tb
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
       
 
 
              
              Params
 
              
                
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bus32_big_dut.params"/>
 
 
 
 
             
              
 
 
              
              Bfm
 
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
 
              Verilog
              
              
 
              
              common:*common:*
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/wb_uart16550_bus32_big_tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/wb_uart16550_bus32_big_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_big_tb`
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49	131	jt_eaton
50
51
52
53	135	jt_eaton
54			`gen_verilog`
55			`104.0`
56			`none`
57			`:common:`
58			`tools/verilog/gen_verilog`
59
60
61			`destination`
62			`wb_uart16550_bus32_big_tb`
63
64
65
66	131	jt_eaton
67
68
69	135	jt_eaton
70	131	jt_eaton
71
72
73	135	jt_eaton
74
75			`UART_MODEL_CLKCNT4'b1100`
76			`UART_MODEL_SIZE4`
77
78	131	jt_eaton
79
80
81	135	jt_eaton
82	131	jt_eaton
83
84	135	jt_eaton
85			`Params`
86	131	jt_eaton
87	135	jt_eaton
88
89			`ipxact:library="wishbone"`
90			`ipxact:name="wb_uart16550"`
91			`ipxact:version="bus32_big_dut.params"/>`
92	131	jt_eaton
93
94
95
96	135	jt_eaton
97
98	131	jt_eaton
99
100	135	jt_eaton
101			`Bfm`
102	131	jt_eaton
103	135	jt_eaton
104			`ipxact:library="wishbone"`
105			`ipxact:name="wb_uart16550"`
106			`ipxact:version="bfm.design"/>`
107
108	131	jt_eaton
109
110	135	jt_eaton
111			`icarus`
112
113
114			`ipxact:library="Testbench"`
115			`ipxact:name="toolflow"`
116			`ipxact:version="icarus"/>`
117
118
119	131	jt_eaton
120
121
122
123	135	jt_eaton
124			`headersheaders`
125	131	jt_eaton
126	135	jt_eaton	`Verilog`
127
128
129	131	jt_eaton
130	135	jt_eaton
131			`common:common:`
132	131	jt_eaton
133	135	jt_eaton	`Verilog`
134
135
136			`fs-common`
137
138
139	131	jt_eaton
140
141
142	135	jt_eaton
143			`sim:Simulation:`
144	131	jt_eaton
145	135	jt_eaton	`Verilog`
146
147
148			`fs-sim`
149
150
151	131	jt_eaton
152	135	jt_eaton
153			`lint:Lint:`
154			`Verilog`
155
156
157			`fs-lint`
158
159
160	131	jt_eaton
161
162	135	jt_eaton
163	131	jt_eaton
164
165
166
167
168	135	jt_eaton
169	131	jt_eaton
170
171
172
173	135	jt_eaton
174	131	jt_eaton
175	135	jt_eaton
176			`fs-common`
177	131	jt_eaton
178	135	jt_eaton
179
180			`../verilog/tb.ext`
181			`verilogSourcefragment`
182
183	131	jt_eaton
184	135	jt_eaton
185	131	jt_eaton
186
187
188	135	jt_eaton
189			`fs-sim`
190	131	jt_eaton
191	135	jt_eaton
192
193			`../verilog/common/wb_uart16550_bus32_big_tb`
194			`verilogSourcemodule`
195
196	131	jt_eaton
197	135	jt_eaton
198	131	jt_eaton
199
200	135	jt_eaton
201			`fs-lint`
202	131	jt_eaton
203	135	jt_eaton
204
205			`../verilog/common/wb_uart16550_bus32_big_tb`
206			`verilogSourcemodule`
207
208	131	jt_eaton
209
210
211	135	jt_eaton
212	131	jt_eaton
213
214
215	135	jt_eaton
216	131	jt_eaton
217
218
219	135	jt_eaton

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_big_tb.xml] - Blame information for rev 135