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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_uart16550
def_tb
 
 
 
 
 
 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      wb_uart16550_def_tb
    
  

 
 
 
 
 
 

 
 

 
 

    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
 
 
       
 
 
              
              Params
              
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="def_dut.params"/>
              
              
 
 
              
              Bfm
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
              Verilog
              
              
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
 
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/wb_uart16550_def_tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/wb_uart16550_def_tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`def_tb`
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49	131	jt_eaton
50	135	jt_eaton
51			`gen_verilog`
52			`104.0`
53			`none`
54			`:common:`
55			`tools/verilog/gen_verilog`
56
57
58			`destination`
59			`wb_uart16550_def_tb`
60
61
62
63	131	jt_eaton
64
65
66
67
68
69	135	jt_eaton
70	131	jt_eaton
71
72	135	jt_eaton
73	131	jt_eaton
74
75	135	jt_eaton
76			`UART_MODEL_CLKCNT4'b1100`
77			`UART_MODEL_SIZE4`
78
79	131	jt_eaton
80
81
82
83
84	135	jt_eaton
85	131	jt_eaton
86
87	135	jt_eaton
88			`Params`
89
90
91			`ipxact:library="wishbone"`
92			`ipxact:name="wb_uart16550"`
93			`ipxact:version="def_dut.params"/>`
94
95
96	131	jt_eaton
97
98	135	jt_eaton
99			`Bfm`
100
101			`ipxact:library="wishbone"`
102			`ipxact:name="wb_uart16550"`
103			`ipxact:version="bfm.design"/>`
104
105	131	jt_eaton
106
107	135	jt_eaton
108			`icarus`
109
110
111			`ipxact:library="Testbench"`
112			`ipxact:name="toolflow"`
113			`ipxact:version="icarus"/>`
114
115
116	131	jt_eaton
117
118
119
120	135	jt_eaton
121			`headersheaders`
122			`Verilog`
123
124
125	131	jt_eaton
126
127
128	135	jt_eaton
129			`common:common:`
130			`Verilog`
131
132
133			`fs-common`
134
135	131	jt_eaton
136	135	jt_eaton
137	131	jt_eaton
138
139	135	jt_eaton
140			`sim:Simulation:`
141			`Verilog`
142
143
144			`fs-sim`
145
146
147	131	jt_eaton
148	135	jt_eaton
149			`lint:Lint:`
150			`Verilog`
151
152
153			`fs-lint`
154
155
156	131	jt_eaton
157
158	135	jt_eaton
159	131	jt_eaton
160
161
162
163
164
165	135	jt_eaton
166	131	jt_eaton
167
168
169	135	jt_eaton
170	131	jt_eaton
171
172	135	jt_eaton
173			`fs-common`
174	131	jt_eaton
175	135	jt_eaton
176
177			`../verilog/tb.ext`
178			`verilogSourcefragment`
179
180	131	jt_eaton
181	135	jt_eaton
182	131	jt_eaton
183
184
185
186
187	135	jt_eaton
188			`fs-sim`
189	131	jt_eaton
190	135	jt_eaton
191
192			`../verilog/common/wb_uart16550_def_tb`
193			`verilogSourcemodule`
194
195	131	jt_eaton
196
197
198	135	jt_eaton
199	131	jt_eaton
200
201	135	jt_eaton
202			`fs-lint`
203	131	jt_eaton
204	135	jt_eaton
205
206			`../verilog/common/wb_uart16550_def_tb`
207			`verilogSourcemodule`
208
209	131	jt_eaton
210
211	135	jt_eaton
212	131	jt_eaton
213
214
215
216	135	jt_eaton
217	131	jt_eaton
218
219
220
221	135	jt_eaton

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_def_tb.xml] - Blame information for rev 135