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[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
valentfx.com
fpgas
logipi_T6502
default
 
 

 

  gen_ise_filelist
  104.0
  none
  
    :*Synthesis:*
  
  tools/sys/gen_child_filelist
  
    
      top
    
    
      suffix
      ISE
    
    
      leader
      "verilog work "
    
    
      overlay_src_ven
      opencores.org
    
    
      overlay_src_lib
      cde
    
    
      overlay_des_ven
      valentfx.com
    
    
      overlay_des_lib
      logipi
    
 
  

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      logipi_T6502_default
    
  

 

 
 
 
 
 
 
 
 
 
 A_CLK
  
  
      
  
    
          
          PAD_in
          
          A_CLK
          
          
    
 
        
      
  
 
 
 
 
 
 
 SW
  
 
  
      
  
    
          
          PAD_in
          
          SW
          10
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 BTN
  
 
  
      
  
    
          
          PAD_in
          
          BTN
          10
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 LED
  
 
  
      
  
    
          
          PAD_out
          
          LED
          10
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 PMOD1
  
 
  
      
  
    
          
          PAD_io
          
          PMOD1
          70
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 PMOD2
  
 
  
      
  
    
          
          PAD_out
          
          PMOD2
          70
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 PMOD3
  
 
  
      
  
    
          
          PAD_out
          
          PMOD3
          70
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 PMOD4
  
 
  
      
  
    
          
          PAD_out
          
          PMOD4
          70
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 SYS_SPI_SCK
  
 
  
      
  
    
          
          PAD_in
          
          SYS_SPI_SCK
          
          
    
 
        
      
 
 
  
 
 
 
 
  SYS_SPI_MISO
  
 
  
      
  
    
          
          PAD_out
          
          SYS_SPI_MISO
          
          
    
 
        
      
 
 
  
 
 
 
 
 
  SYS_SPI_MOSI
  
 
  
      
  
    
          
          PAD_in
          
          SYS_SPI_MOSI
          
          
    
 
        
      
 
 
  
 
 
 
 
 
  RP_SPI_CE0N
  
 
  
      
  
    
          
          PAD_in
          
          RP_SPI_CE0N
          
          
    
 
        
      
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

 
 

    CLOCK_PLL_MULT2
    CLOCK_PLL_DIV4
    CLOCK_PLL_SIZE4
    CLOCK_SRC0
    RESET_SENSE1
    CHIP_ID32'hf1c2e093

 
 
 
 

 
 
        Hierarchical2
        
 
 
 
 
 
     Hierarchical
     
 
 
 
 
     Padring_jtag
     
  
 
  
 
 
 
  
 
 
    
       Hierarchical2
       Hierarchical2
    
 
   
       Hierarchical:*Simulation:*
       Hierarchical
   
 
 
   
       Padring_jtag:*Simulation:*
       Padring_jtag
   
 
 
    
              verilog:*Simulation:*
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
    
 
 
 
    
      common:*common:*
      Verilog
      
      fs-common
    
 
  
    sim:*Simulation:*
    Verilog
    
    fs-sim
  
 
 
  
    syn:*Synthesis:*
    Verilog
    
    fs-sim
  
 
 
  
    doc:*Simulation:*
    
    
                         ipxact:library="Testbench"
                         ipxact:name="toolflow"
                         ipxact:version="documentation"/>
    
    :*Documentation:*
    Verilog
  
 
 
 
 
 
 
 

 
 
A_CLK
wire
in

 
 
 SW
wire
in
 
 
 BTN
wire
in
 
 
 LED
wire
out
 
 
 PMOD1
wire
inout
 
 
 PMOD2
wire
inout
 
 
 PMOD3
wire
inout
 
 
 PMOD4
wire
inout
 
 
 SYS_SPI_SCK
wire
in
 
 
  SYS_SPI_MISO
wire
out
  
 
  SYS_SPI_MOSI
wire
in
  
 
  RP_SPI_CE0N
wire
in

 
 
 
 
 
 
 
 
 

 
 
 
 
  
 
 
 
    
      fs-pad
 
 
      
        
        ../verilog/pad/top.fpga
        verilogSourcemodule
      
 
 
      
        ../views/pad/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/logipi_T6502_default
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/logipi_T6502_default
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
    
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [rtl/] [xml/] [Nexys2_T6502_default.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`valentfx.com`
37			`fpgas`
38			`logipi_T6502`
39			`default`
40
41
42
43
44
45			`gen_ise_filelist`
46			`104.0`
47			`none`
48
49			`:Synthesis:`
50
51			`tools/sys/gen_child_filelist`
52
53
54			`top`
55
56
57			`suffix`
58			`ISE`
59
60
61			`leader`
62			`"verilog work "`
63
64
65			`overlay_src_ven`
66			`opencores.org`
67
68
69			`overlay_src_lib`
70			`cde`
71
72
73			`overlay_des_ven`
74			`valentfx.com`
75
76
77			`overlay_des_lib`
78			`logipi`
79
80
81
82
83
84
85			`gen_verilog`
86			`104.0`
87			`none`
88			`:common:`
89			`tools/verilog/gen_verilog`
90
91
92			`destination`
93			`logipi_T6502_default`
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108			`A_CLK`
109
110
111
112
113
114
115			`PAD_in`
116
117			`A_CLK`
118
119
120
121
122
123
124
125
126
127
128
129
130
131			`SW`
132
133
134
135
136
137
138
139			`PAD_in`
140
141			`SW`
142			`10`
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158			`BTN`
159
160
161
162
163
164
165
166			`PAD_in`
167
168			`BTN`
169			`10`
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185			`LED`
186
187
188
189
190
191
192
193			`PAD_out`
194
195			`LED`
196			`10`
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212			`PMOD1`
213
214
215
216
217
218
219
220			`PAD_io`
221
222			`PMOD1`
223			`70`
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240			`PMOD2`
241
242
243
244
245
246
247
248			`PAD_out`
249
250			`PMOD2`
251			`70`
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268			`PMOD3`
269
270
271
272
273
274
275
276			`PAD_out`
277
278			`PMOD3`
279			`70`
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296			`PMOD4`
297
298
299
300
301
302
303
304			`PAD_out`
305
306			`PMOD4`
307			`70`
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322			`SYS_SPI_SCK`
323
324
325
326
327
328
329
330			`PAD_in`
331
332			`SYS_SPI_SCK`
333
334
335
336
337
338
339
340
341
342
343
344
345
346			`SYS_SPI_MISO`
347
348
349
350
351
352
353
354			`PAD_out`
355
356			`SYS_SPI_MISO`
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371			`SYS_SPI_MOSI`
372
373
374
375
376
377
378
379			`PAD_in`
380
381			`SYS_SPI_MOSI`
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396			`RP_SPI_CE0N`
397
398
399
400
401
402
403
404			`PAD_in`
405
406			`RP_SPI_CE0N`
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449			`CLOCK_PLL_MULT2`
450			`CLOCK_PLL_DIV4`
451			`CLOCK_PLL_SIZE4`
452			`CLOCK_SRC0`
453			`RESET_SENSE1`
454			`CHIP_ID32'hf1c2e093`
455
456
457
458
459
460
461
462
463			`Hierarchical2`
464
465
466
467
468
469
470			`Hierarchical`
471
472
473
474
475
476			`Padring_jtag`
477
478
479
480
481
482
483
484
485
486
487
488			`Hierarchical2`
489			`Hierarchical2`
490
491
492
493			`Hierarchical:Simulation:`
494			`Hierarchical`
495
496
497
498
499			`Padring_jtag:Simulation:`
500			`Padring_jtag`
501
502
503
504
505			`verilog:Simulation:`
506
507
508			`ipxact:library="Testbench"`
509			`ipxact:name="toolflow"`
510			`ipxact:version="verilog"/>`
511
512
513
514
515
516
517			`common:common:`
518			`Verilog`
519
520			`fs-common`
521
522
523
524			`sim:Simulation:`
525			`Verilog`
526
527			`fs-sim`
528
529
530
531
532			`syn:Synthesis:`
533			`Verilog`
534
535			`fs-sim`
536
537
538
539
540			`doc:Simulation:`
541
542
543			`ipxact:library="Testbench"`
544			`ipxact:name="toolflow"`
545			`ipxact:version="documentation"/>`
546
547			`:Documentation:`
548			`Verilog`
549
550
551
552
553
554
555
556
557
558
559
560			`A_CLK`
561			`wire`
562			`in`
563
564
565
566			`SW`
567			`wire`
568			`in`
569
570
571			`BTN`
572			`wire`
573			`in`
574
575
576			`LED`
577			`wire`
578			`out`
579
580
581			`PMOD1`
582			`wire`
583			`inout`
584
585
586			`PMOD2`
587			`wire`
588			`inout`
589
590
591			`PMOD3`
592			`wire`
593			`inout`
594
595
596			`PMOD4`
597			`wire`
598			`inout`
599
600
601			`SYS_SPI_SCK`
602			`wire`
603			`in`
604
605
606			`SYS_SPI_MISO`
607			`wire`
608			`out`
609
610
611			`SYS_SPI_MOSI`
612			`wire`
613			`in`
614
615
616			`RP_SPI_CE0N`
617			`wire`
618			`in`
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639			`fs-pad`
640
641
642
643
644			`../verilog/pad/top.fpga`
645			`verilogSourcemodule`
646
647
648
649
650			`../views/pad/`
651			`verilogSourcelibraryDir`
652
653
654
655
656
657
658
659
660
661			`fs-sim`
662
663
664
665			`../verilog/copyright`
666			`verilogSourceinclude`
667
668
669
670
671			`../verilog/common/logipi_T6502_default`
672			`verilogSourcemodule`
673
674
675
676			`dest_dir`
677			`../views/sim/`
678			`verilogSourcelibraryDir`
679
680
681
682
683
684
685
686
687			`fs-syn`
688
689
690
691			`../verilog/copyright`
692			`verilogSourceinclude`
693
694
695
696
697			`../verilog/common/logipi_T6502_default`
698			`verilogSourcemodule`
699
700
701
702			`dest_dir`
703			`../views/syn/`
704			`verilogSourcelibraryDir`
705
706
707
708
709
710
711
712
713
714			`fs-lint`
715
716
717			`dest_dir`
718			`../views/syn/`
719			`verilogSourcelibraryDir`
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
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745