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[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 135

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assign A_CLK   = clk;
 
 
pullup pu_jtag ( JTAG_TDO );
 
 
reg [1:0] SW_reg;
reg [1:0] BTN_reg;
 
initial
begin
SW_reg  = 2'b00;
BTN_reg = 2'b00;
end
 
assign SW = SW_reg;
assign BTN = BTN_reg;
assign STOP = 1'b0;
assign BAD = 1'b0;
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton	`assign A_CLK = clk;`
2
3
4			`pullup pu_jtag ( JTAG_TDO );`
5
6
7			`reg [1:0] SW_reg;`
8			`reg [1:0] BTN_reg;`
9
10			`initial`
11			`begin`
12			`SW_reg = 2'b00;`
13			`BTN_reg = 2'b00;`
14			`end`
15
16			`assign SW = SW_reg;`
17			`assign BTN = BTN_reg;`
18			`assign STOP = 1'b0;`
19			`assign BAD = 1'b0;`
20
21

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[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 135