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[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
valentfx.com
fpgas
logipi_T6502
default_tb
 
 
 
 
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      logipi_T6502_default_tb
    
  

 
 
 

 
 
 
 
 


    JTAG_MODEL_DIVCNT 4'h4     
    JTAG_MODEL_SIZE   4        
    SPI_CLKCNT  8'h34  
    SPI_SIZE    8       
 

       
 
 
 
              
              Params
              
              
                                   ipxact:library="fpgas"
                                   ipxact:name="logipi_T6502"
                                   ipxact:version="default_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   ipxact:library="fpgas"
                                   ipxact:name="logipi_T6502"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 

 
 
 
  
 
 
 
    
      fs-common
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
 
    
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/logipi_T6502_default_tb
        verilogSourcemodule
      
 
    
 
 
 
 
 
 
 
  
 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`valentfx.com`
37			`fpgas`
38			`logipi_T6502`
39			`default_tb`
40
41
42
43
44
45
46
47
48			`gen_verilog`
49			`104.0`
50			`none`
51			`:common:`
52			`tools/verilog/gen_verilog`
53
54
55			`destination`
56			`logipi_T6502_default_tb`
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71			`JTAG_MODEL_DIVCNT 4'h4`
72			`JTAG_MODEL_SIZE 4`
73			`SPI_CLKCNT 8'h34`
74			`SPI_SIZE 8`
75
76
77
78
79
80
81
82			`Params`
83
84
85			`ipxact:library="fpgas"`
86			`ipxact:name="logipi_T6502"`
87			`ipxact:version="default_dut.params"/>`
88
89
90
91
92
93
94			`Bfm`
95
96			`ipxact:library="fpgas"`
97			`ipxact:name="logipi_T6502"`
98			`ipxact:version="bfm.design"/>`
99
100
101
102
103
104			`icarus`
105
106
107			`ipxact:library="Testbench"`
108			`ipxact:name="toolflow"`
109			`ipxact:version="icarus"/>`
110
111
112
113
114
115
116
117			`common:common:`
118			`Verilog`
119
120
121			`fs-common`
122
123
124
125
126
127			`sim:Simulation:`
128			`Verilog`
129
130
131			`fs-sim`
132
133
134
135
136			`lint:Lint:`
137			`Verilog`
138
139
140			`fs-lint`
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157			`fs-common`
158
159
160
161
162			`../verilog/tb.ext`
163			`verilogSourcefragment`
164
165
166
167
168
169
170
171
172
173
174			`fs-sim`
175
176
177
178			`../verilog/common/logipi_T6502_default_tb`
179			`verilogSourcemodule`
180
181
182
183
184
185
186
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [sim/] [testbenches/] [xml/] [Nexys2_T6502_default_tb.xml] - Blame information for rev 135