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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [syn/] [chips/] [xml/] [Nexys2_T6502_chip.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
valentfx.com
fpgas
logipi_T6502
chip
 
 
 
  
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSource
        include
      
 
 
    
 
  
 

 
 
  
 
    
    syn:*Synthesis:*
    Verilog
    
    
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton
2
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31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`valentfx.com`
37			`fpgas`
38			`logipi_T6502`
39			`chip`
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46			`fs-syn`
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50			`../verilog/copyright.v`
51			`verilogSource`
52			`include`
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66			`syn:Synthesis:`
67			`Verilog`
68
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [syn/] [chips/] [xml/] [Nexys2_T6502_chip.xml] - Blame information for rev 135