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[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [syn/] [ise/] [logipi_T6502_kim_2/] [xml/] [Nexys2_T6502_kim_2.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
valentfx.com
fpgas
logipi_T6502
kim_2
 
 

 
 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
   
      local_parameters
    
    
      destination
      top.T6502_kim_2.syn
    
  

 
 
 

 
 
 
 
  
 
 
 
    
      fs-syn
 
      
        
        ../verilog/syn/top.T6502_kim_2.syn
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 

 
 
 
 
                
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
 
  
 
    
    Hierarchical
     Hierarchical
    
 
   
     Pad_Ring
          
     
                          ipxact:library="fpgas"
                          ipxact:name="logipi_T6502"
                          ipxact:version="padring"/>
     
 
    
 
 
    
     Chip
     
     
                          ipxact:library="fpgas"
                          ipxact:name="logipi_T6502"
                          ipxact:version="chip"/>
     
    
 
     
     ise
     
     
                          ipxact:library="Testbench"
                          ipxact:name="toolflow"
                          ipxact:version="ise"/>
     
     
 
    
    syn:*Synthesis:*
 
    Verilog
    
    fs-syn
    
 
 
 
 

 
 

 
 
 
 
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`valentfx.com`
37			`fpgas`
38			`logipi_T6502`
39			`kim_2`
40
41
42
43
44
45
46
47			`gen_verilog_syn`
48			`104.0`
49			`none`
50			`:Synthesis:`
51			`tools/verilog/gen_verilog`
52
53
54			`local_parameters`
55
56
57			`destination`
58			`top.T6502_kim_2.syn`
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75			`fs-syn`
76
77
78
79			`../verilog/syn/top.T6502_kim_2.syn`
80			`verilogSourcemodule`
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100			`Hierarchical`
101
102
103
104
105
106
107
108
109
110
111
112
113			`Hierarchical`
114			`Hierarchical`
115
116
117
118			`Pad_Ring`
119
120
121			`ipxact:library="fpgas"`
122			`ipxact:name="logipi_T6502"`
123			`ipxact:version="padring"/>`
124
125
126
127
128
129
130			`Chip`
131
132
133			`ipxact:library="fpgas"`
134			`ipxact:name="logipi_T6502"`
135			`ipxact:version="chip"/>`
136
137
138
139
140			`ise`
141
142
143			`ipxact:library="Testbench"`
144			`ipxact:name="toolflow"`
145			`ipxact:version="ise"/>`
146
147
148
149
150			`syn:Synthesis:`
151
152			`Verilog`
153
154			`fs-syn`
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [fpgas/] [ip/] [logipi_T6502/] [syn/] [ise/] [logipi_T6502_kim_2/] [xml/] [Nexys2_T6502_kim_2.xml] - Blame information for rev 135