URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [logipi/] [ip/] [clock/] [rtl/] [verilog/] [syn/] [clock_sys.v] - Blame information for rev 135

Details | Compare with Previous | View Log


module
cde_clock_sys
#(parameter   FREQ        = 48,
              PLL_MULT    =  4,
              PLL_DIV     =  2,
              PLL_SIZE    =  4,
              CLOCK_SRC   =  0,
              RESET_SENSE =  0
)
 
(
input  wire   a_clk_pad_in,
input  wire   b_clk_pad_in,
input  wire   pwron_pad_in,
 
output wire      div_clk_out,
 
 
output  reg   one_usec,
output  wire   reset
 
);
 
wire      ckIn;
reg       ref_reset;
 
reg [6:0] counter;
reg [3:0] reset_cnt;
 
wire      pwron_reset;
   wire      dll_reset;
 
 
  wire ckOut;
 
 
 
generate
 
if( CLOCK_SRC)
 
  begin
  assign ckIn = b_clk_pad_in;
  end
else
  begin
  assign ckIn = a_clk_pad_in;
  end
 
endgenerate
 
 
generate
 
if( RESET_SENSE)
 
  begin
  assign pwron_reset = !pwron_pad_in;
  end
else
  begin
  assign pwron_reset = pwron_pad_in;
  end
 
endgenerate
 
 
 
 
 
 
 
 
 
 
 
always@(posedge ckIn or posedge pwron_reset)
  if( pwron_reset)   reset_cnt     <= 4'b1111;
  else
  if(|reset_cnt)     reset_cnt     <= reset_cnt-4'b0001;
  else               reset_cnt     <= 4'b0000;
 
 
 
always@(posedge ckIn or posedge pwron_reset)
  if( pwron_reset)   ref_reset     <= 1'b1;
  else               ref_reset     <= |reset_cnt;
 
 
 
 
 
 
 
 
always@(posedge ckOut)
  if(dll_reset)
       begin
       one_usec  <=  1'b0;
       counter   <=  FREQ;
       end
  else if(counter == 7'b0000001)
       begin
       one_usec  <= !one_usec;
       counter   <=  FREQ;
       end
  else
       begin
       one_usec  <=  one_usec;
       counter   <=  counter -7'b0000001;
       end
 
 
wire    ckOut_pre;
 
DCM_SP #(
     .CLKDV_DIVIDE         (2.0),
     .CLKFX_DIVIDE         (1),
     .CLKFX_MULTIPLY       (4),
     .CLKIN_DIVIDE_BY_2    ("FALSE"),
 
 
     .CLKIN_PERIOD         (20.0),
     .CLKOUT_PHASE_SHIFT   ("NONE"),
     .CLK_FEEDBACK         ("2X"),
 
     .DESKEW_ADJUST        ("SYSTEM_SYNCHRONOUS"),
     .PHASE_SHIFT          (0),
     .STARTUP_WAIT         ("FALSE")
 
) DCM_SP_inst    (
      .CLKIN     (ckIn),
      .CLKFB     (ckOut),
      .CLK0      (),
      .CLK90     (),
      .CLK180    (),
      .CLK270    (),
      .CLK2X     (ckOut_pre),
      .CLK2X180  (),
      .CLKFX     (),
      .CLKFX180  (),
      .CLKDV     (),
 
 
 
      .PSDONE    (),
      .STATUS    (),
      .PSCLK     (1'b0),
      .PSEN      (1'b0),
      .PSINCDEC  (1'b0),
 
      .LOCKED    (),
 
      .RST       (1'b0)
   );
 
 
  BUFG
  BUFG_inst (
            .I(ckOut_pre),      // Clock buffer input
            .O(ckOut)           // Clock buffer output
            );
 
 
   assign div_clk_out = ckOut;
 
 
 
 
 
 
cde_sync_with_reset
  #(.WIDTH  (1),
    .DEPTH  (2),
    .RST_VAL(1'b1)
   )
  ref_rsync(
    .clk                 (div_clk_out),
    .reset_n             (!pwron_reset),
    .data_in             (ref_reset),
    .data_out            (reset)
       );
 
 
 
 
cde_sync_with_reset
  #(.WIDTH  (1),
    .DEPTH  (2),
    .RST_VAL(1'b1)
   )
  dll_rsync(
    .clk                 (ckOut),
    .reset_n             (!pwron_reset),
    .data_in             (ref_reset),
    .data_out            (dll_reset)
       );
 
 
 
endmodule

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [valentfx.com/] [logipi/] [ip/] [clock/] [rtl/] [verilog/] [syn/] [clock_sys.v] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`module`
2			`cde_clock_sys`
3			`#(parameter FREQ = 48,`
4			`PLL_MULT = 4,`
5			`PLL_DIV = 2,`
6			`PLL_SIZE = 4,`
7			`CLOCK_SRC = 0,`
8			`RESET_SENSE = 0`
9			`)`
10
11			`(`
12			`input wire a_clk_pad_in,`
13			`input wire b_clk_pad_in,`
14			`input wire pwron_pad_in,`
15
16			`output wire div_clk_out,`
17
18
19			`output reg one_usec,`
20			`output wire reset`
21
22			`);`
23
24			`wire ckIn;`
25			`reg ref_reset;`
26
27			`reg [6:0] counter;`
28			`reg [3:0] reset_cnt;`
29
30			`wire pwron_reset;`
31			`wire dll_reset;`
32
33
34			`wire ckOut;`
35
36
37
38			`generate`
39
40			`if( CLOCK_SRC)`
41
42			`begin`
43			`assign ckIn = b_clk_pad_in;`
44			`end`
45			`else`
46			`begin`
47			`assign ckIn = a_clk_pad_in;`
48			`end`
49
50			`endgenerate`
51
52
53			`generate`
54
55			`if( RESET_SENSE)`
56
57			`begin`
58			`assign pwron_reset = !pwron_pad_in;`
59			`end`
60			`else`
61			`begin`
62			`assign pwron_reset = pwron_pad_in;`
63			`end`
64
65			`endgenerate`
66
67
68
69
70
71
72
73
74
75
76
77			`always@(posedge ckIn or posedge pwron_reset)`
78			`if( pwron_reset) reset_cnt <= 4'b1111;`
79			`else`
80			`if(\|reset_cnt) reset_cnt <= reset_cnt-4'b0001;`
81			`else reset_cnt <= 4'b0000;`
82
83
84
85			`always@(posedge ckIn or posedge pwron_reset)`
86			`if( pwron_reset) ref_reset <= 1'b1;`
87			`else ref_reset <= \|reset_cnt;`
88
89
90
91
92
93
94
95
96			`always@(posedge ckOut)`
97			`if(dll_reset)`
98			`begin`
99			`one_usec <= 1'b0;`
100			`counter <= FREQ;`
101			`end`
102			`else if(counter == 7'b0000001)`
103			`begin`
104			`one_usec <= !one_usec;`
105			`counter <= FREQ;`
106			`end`
107			`else`
108			`begin`
109			`one_usec <= one_usec;`
110			`counter <= counter -7'b0000001;`
111			`end`
112
113
114			`wire ckOut_pre;`
115
116			`DCM_SP #(`
117			`.CLKDV_DIVIDE (2.0),`
118			`.CLKFX_DIVIDE (1),`
119			`.CLKFX_MULTIPLY (4),`
120			`.CLKIN_DIVIDE_BY_2 ("FALSE"),`
121
122
123			`.CLKIN_PERIOD (20.0),`
124			`.CLKOUT_PHASE_SHIFT ("NONE"),`
125			`.CLK_FEEDBACK ("2X"),`
126
127			`.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),`
128			`.PHASE_SHIFT (0),`
129			`.STARTUP_WAIT ("FALSE")`
130
131			`) DCM_SP_inst (`
132			`.CLKIN (ckIn),`
133			`.CLKFB (ckOut),`
134			`.CLK0 (),`
135			`.CLK90 (),`
136			`.CLK180 (),`
137			`.CLK270 (),`
138			`.CLK2X (ckOut_pre),`
139			`.CLK2X180 (),`
140			`.CLKFX (),`
141			`.CLKFX180 (),`
142			`.CLKDV (),`
143
144
145
146			`.PSDONE (),`
147			`.STATUS (),`
148			`.PSCLK (1'b0),`
149			`.PSEN (1'b0),`
150			`.PSINCDEC (1'b0),`
151
152			`.LOCKED (),`
153
154			`.RST (1'b0)`
155			`);`
156
157
158			`BUFG`
159			`BUFG_inst (`
160			`.I(ckOut_pre), // Clock buffer input`
161			`.O(ckOut) // Clock buffer output`
162			`);`
163
164
165			`assign div_clk_out = ckOut;`
166
167
168
169
170
171
172			`cde_sync_with_reset`
173			`#(.WIDTH (1),`
174			`.DEPTH (2),`
175			`.RST_VAL(1'b1)`
176			`)`
177			`ref_rsync(`
178			`.clk (div_clk_out),`
179			`.reset_n (!pwron_reset),`
180			`.data_in (ref_reset),`
181			`.data_out (reset)`
182			`);`
183
184
185
186
187			`cde_sync_with_reset`
188			`#(.WIDTH (1),`
189			`.DEPTH (2),`
190			`.RST_VAL(1'b1)`
191			`)`
192			`dll_rsync(`
193			`.clk (ckOut),`
194			`.reset_n (!pwron_reset),`
195			`.data_in (ref_reset),`
196			`.data_out (dll_reset)`
197			`);`
198
199
200
201			`endmodule`