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jt_eaton |
/**********************************************************************/
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/* */
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/* ------- */
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/* / SOC \ */
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/* / GEN \ */
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/* / TARGET \ */
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/* ============== */
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/* | | */
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/* |____________| */
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/* */
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/* Jtag tap controller for xilinx spartan 3e fpga */
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/* */
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/* */
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/* Author(s): */
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/* - John Eaton, jt_eaton@opencores.org */
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/* */
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/**********************************************************************/
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/* */
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/* Copyright (C) <2010> <Ouabache Design Works> */
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/* */
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/* This source file may be used and distributed without */
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/* restriction provided that this copyright statement is not */
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/* removed from the file and that any derivative work contains */
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/* the original copyright notice and the associated disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it */
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/* and/or modify it under the terms of the GNU Lesser General */
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/* Public License as published by the Free Software Foundation; */
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/* either version 2.1 of the License, or (at your option) any */
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/* later version. */
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/* */
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/* This source is distributed in the hope that it will be */
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/* useful, but WITHOUT ANY WARRANTY; without even the implied */
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/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
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/* PURPOSE. See the GNU Lesser General Public License for more */
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/* details. */
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/* */
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/* You should have received a copy of the GNU Lesser General */
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/* Public License along with this source; if not, download it */
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/* from http://www.opencores.org/lgpl.shtml */
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/* */
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/**********************************************************************/
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//////////////////////////////////////////////////////////////////////
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// //
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// This file is a wrapper for the various Xilinx internal BSCAN //
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// TAP devices. It is designed to take the place of a separate TAP //
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// controller in Xilinx systems, to allow a user to access a CPU //
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// debug module (such as that of the OR1200) through the FPGA's //
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// dedicated JTAG / configuration port. //
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// //
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//////////////////////////////////////////////////////////////////////
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//
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// Note that the SPARTAN BSCAN controllers have more than one channel.
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// This implementation always uses channel 1, this is not configurable.
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// If you want to use another channel, then it is probably because you
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// want to attach multiple devices to the BSCAN device, which means
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// you'll be making changes to this file anyway.
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module cde_jtag_tap
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#(parameter CHIP_ID_VAL=32'h00000000 )
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(
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input wire tdo_i,
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output wire shiftcapture_dr_clk_o,
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output wire tdi_o,
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output wire test_logic_reset_o,
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output wire shift_dr_o,
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output wire capture_dr_o,
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output wire update_dr_clk_o,
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output wire select_o,
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input wire aux_tdo_i,
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output wire aux_shiftcapture_dr_clk_o,
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output wire aux_tdi_o,
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output wire aux_test_logic_reset_o,
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output wire aux_shift_dr_o,
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output wire aux_capture_dr_o,
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output wire aux_update_dr_clk_o,
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output wire aux_select_o
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);
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wire update_dr_i;
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wire aux_update_dr_i;
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BSCAN_SPARTAN6
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#(1)
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BSCAN_SPARTAN6_inst1 (
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.CAPTURE (capture_dr_o), // CAPTURE output from TAP controller
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.DRCK (user1_clk_i), // shiftcapture clk for USER1 functions
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.RESET (test_logic_reset_o), // Reset output from TAP controller
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.RUNTEST ( ),
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.SEL (select_o), // USER1 active output
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.SHIFT (shift_dr_o), // SHIFT output from TAP controller
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.TCK (),
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.TDI (tdi_o), // TDI output from TAP controller
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.TMS (),
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.UPDATE (update_dr_i), // UPDATE output from TAP controller
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.TDO (tdo_i) // Data input for USER1 function
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);
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BSCAN_SPARTAN6
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#(2)
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BSCAN_SPARTAN6_inst2 (
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.CAPTURE (aux_capture_dr_o), // CAPTURE output from TAP controller
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.DRCK (user2_clk_i), // shiftcapture clk for USER1 functions
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.RESET (aux_test_logic_reset_o), // Reset output from TAP controller
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.RUNTEST ( ),
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.SEL (aux_select_o), // USER1 active output
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.SHIFT (aux_shift_dr_o), // SHIFT output from TAP controller
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.TCK (),
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.TDI (aux_tdi_o), // TDI output from TAP controller
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.TMS (),
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.UPDATE (aux_update_dr_i), // UPDATE output from TAP controller
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.TDO (aux_tdo_i) // Data input for USER2 function
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);
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BUFG
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update_buf (
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.O (update_dr_clk_o), // Clock buffer output
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.I (update_dr_i) // Clock buffer input
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);
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BUFG
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aux_update_buf (
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.O (aux_update_dr_clk_o), // Clock buffer output
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.I (aux_update_dr_i) // Clock buffer input
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);
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BUFG
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user1_clk_buf (
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.O (shiftcapture_dr_clk_o), // Clock buffer output
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.I (user1_clk_i ) // Clock buffer input
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);
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BUFG
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user2_clk_buf (
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.O (aux_shiftcapture_dr_clk_o), // Clock buffer output
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.I (user2_clk_i ) // Clock buffer input
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);
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endmodule
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