URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [AND/] [demorgan/] [and3.sym] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20031231 1`
2			`L 300 600 600 600 3 0 0 0 -1 -1`
3			`L 300 0 600 0 3 0 0 0 -1 -1`
4			`A 40 300 400 312 97 3 0 0 0 -1 -1`
5			`A 600 400 400 270 76 3 0 0 0 -1 -1`
6			`A 600 200 400 14 76 3 0 0 0 -1 -1`
7			`V 1050 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
8			`P 1100 300 1300 300 1 0 1`
9			`{`
10			`T 1000 300 5 8 0 0 0 0 1`
11			`pinnumber=OUT`
12			`T 1000 300 5 8 0 0 0 0 1`
13			`pinseq=1`
14			`}`
15			`V 250 100 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
16			`P 200 100 0 100 1 0 1`
17			`{`
18			`T 300 100 5 8 0 0 0 0 1`
19			`pinnumber=IN0`
20			`T 300 100 5 8 0 0 0 0 1`
21			`pinseq=2`
22			`}`
23			`V 250 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
24			`P 200 300 0 300 1 0 1`
25			`{`
26			`T 300 300 5 8 0 0 0 0 1`
27			`pinnumber=IN1`
28			`T 300 300 5 8 0 0 0 0 1`
29			`pinseq=3`
30			`}`
31			`V 250 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
32			`P 200 500 0 500 1 0 1`
33			`{`
34			`T 300 500 5 8 0 0 0 0 1`
35			`pinnumber=IN2`
36			`T 300 500 5 8 0 0 0 0 1`
37			`pinseq=4`
38			`}`
39			`T 400 -100 5 10 1 1 0 2 1`
40			`refdes=U?`
41			`T 400 100 5 8 0 0 0 0 1`
42			`device=and`
43			`T 400 200 5 8 0 0 0 0 1`
44			`VERILOG_PORTS=POSITIONAL`