URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [NOR/] [demorgan/] [nor3.sym] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20031231 1`
2			`L 300 600 700 600 3 0 0 0 -1 -1`
3			`L 300 0 700 0 3 0 0 0 -1 -1`
4			`L 300 0 300 600 3 0 0 0 -1 -1`
5			`A 700 300 300 270 180 3 0 0 0 -1 -1`
6			`P 1000 300 1300 300 1 0 1`
7			`{`
8			`T 1000 300 5 8 0 0 0 0 1`
9			`pinnumber=OUT`
10			`T 1000 300 5 8 0 0 0 0 1`
11			`pinseq=1`
12			`}`
13			`V 250 100 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
14			`P 200 100 0 100 1 0 1`
15			`{`
16			`T 300 100 5 8 0 0 0 0 1`
17			`pinnumber=IN0`
18			`T 300 100 5 8 0 0 0 0 1`
19			`pinseq=2`
20			`}`
21			`V 250 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
22			`P 200 300 0 300 1 0 1`
23			`{`
24			`T 300 300 5 8 0 0 0 0 1`
25			`pinnumber=IN1`
26			`T 300 300 5 8 0 0 0 0 1`
27			`pinseq=3`
28			`}`
29			`V 250 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
30			`P 200 500 0 500 1 0 1`
31			`{`
32			`T 300 500 5 8 0 0 0 0 1`
33			`pinnumber=IN2`
34			`T 300 500 5 8 0 0 0 0 1`
35			`pinseq=4`
36			`}`
37			`T 400 -100 5 10 1 1 0 2 1`
38			`refdes=U?`
39			`T 400 100 5 8 0 0 0 0 1`
40			`device=nor`
41			`T 400 200 5 8 0 0 0 0 1`
42			`VERILOG_PORTS=POSITIONAL`