URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [OR/] [demorgan/] [or3.sym] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton	`v 20031231 1`
2			`L 300 600 700 600 3 0 0 0 -1 -1`
3			`L 300 0 700 0 3 0 0 0 -1 -1`
4			`L 300 0 300 600 3 0 0 0 -1 -1`
5			`A 700 300 300 270 180 3 0 0 0 -1 -1`
6			`V 1050 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
7			`P 1100 300 1300 300 1 0 1`
8			`{`
9			`T 1000 300 5 8 0 0 0 0 1`
10			`pinnumber=OUT`
11			`T 1000 300 5 8 0 0 0 0 1`
12			`pinseq=1`
13			`}`
14			`V 250 100 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
15			`P 200 100 0 100 1 0 1`
16			`{`
17			`T 300 100 5 8 0 0 0 0 1`
18			`pinnumber=IN0`
19			`T 300 100 5 8 0 0 0 0 1`
20			`pinseq=2`
21			`}`
22			`V 250 300 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
23			`P 200 300 0 300 1 0 1`
24			`{`
25			`T 300 300 5 8 0 0 0 0 1`
26			`pinnumber=IN1`
27			`T 300 300 5 8 0 0 0 0 1`
28			`pinseq=3`
29			`}`
30			`V 250 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1`
31			`P 200 500 0 500 1 0 1`
32			`{`
33			`T 300 500 5 8 0 0 0 0 1`
34			`pinnumber=IN2`
35			`T 300 500 5 8 0 0 0 0 1`
36			`pinseq=4`
37			`}`
38			`T 400 -100 5 10 1 1 0 2 1`
39			`refdes=U?`
40			`T 400 100 5 8 0 0 0 0 1`
41			`device=or`
42			`T 400 200 5 8 0 0 0 0 1`
43			`VERILOG_PORTS=POSITIONAL`