OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [geda-project.org/] [gEDA/] [logic/] [XOR/] [xor4.sym] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton
v 20031231 1
2
L 400 700 600 700 3 0 0 0 -1 -1
3
L 400 100 600 100 3 0 0 0 -1 -1
4
A 40 400 400 312 97 3 0 0 0 -1 -1
5
A 140 400 400 312 97 3 0 0 0 -1 -1
6
A 600 500 400 270 76 3 0 0 0 -1 -1
7
A 600 300 400 14 76 3 0 0 0 -1 -1
8
L 300 700 300 800 3 0 0 0 -1 -1
9
L 300 100 300 0 3 0 0 0 -1 -1
10
P 1000 400 1300 400 1 0 1
11
{
12
T 1000 400 5 8 0 0 0 0 1
13
pinnumber=OUT
14
T 1000 400 5 8 0 0 0 0 1
15
pinseq=1
16
}
17
P 300 100 0 100 1 0 1
18
{
19
T 300 100 5 8 0 0 0 0 1
20
pinnumber=IN0
21
T 300 100 5 8 0 0 0 0 1
22
pinseq=2
23
}
24
P 300 300 0 300 1 0 1
25
{
26
T 300 300 5 8 0 0 0 0 1
27
pinnumber=IN1
28
T 300 300 5 8 0 0 0 0 1
29
pinseq=3
30
}
31
P 300 500 0 500 1 0 1
32
{
33
T 300 500 5 8 0 0 0 0 1
34
pinnumber=IN2
35
T 300 500 5 8 0 0 0 0 1
36
pinseq=4
37
}
38
P 300 700 0 700 1 0 1
39
{
40
T 300 700 5 8 0 0 0 0 1
41
pinnumber=IN3
42
T 300 700 5 8 0 0 0 0 1
43
pinseq=5
44
}
45
T 400 0 5 10 1 1 0 2 1
46
refdes=U?
47
T 400 100 5 8 0 0 0 0 1
48
device=xor
49
T 400 200 5 8 0 0 0 0 1
50
VERILOG_PORTS=POSITIONAL

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.