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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_host_model/] [rtl/] [verilog/] [logic] - Blame information for rev 135

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always@(posedge clk)
  if(reset)
    begin
      io_host_debug_stats_pcr    <=  1'b0;
      io_host_in_bits            <=  16'h0000;
      io_host_in_valid           <=  1'b0;
      io_host_out_ready          <=  1'b0;
    end
 
assign io_host_clk = clk;
 
 
 
always@(posedge clk)
  if(reset)
    begin
      io_host_clk_edge           <=  1'b0;
    end
  else
    begin
      io_host_clk_edge           <= ! io_host_clk_edge;
    end

Line No.	Rev	Author	Line
1	135	jt_eaton	`always@(posedge clk)`
2			`if(reset)`
3			`begin`
4			`io_host_debug_stats_pcr <= 1'b0;`
5			`io_host_in_bits <= 16'h0000;`
6			`io_host_in_valid <= 1'b0;`
7			`io_host_out_ready <= 1'b0;`
8			`end`
9
10			`assign io_host_clk = clk;`
11
12
13
14			`always@(posedge clk)`
15			`if(reset)`
16			`begin`
17			`io_host_clk_edge <= 1'b0;`
18			`end`
19			`else`
20			`begin`
21			`io_host_clk_edge <= ! io_host_clk_edge;`
22			`end`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_host_model/] [rtl/] [verilog/] [logic] - Blame information for rev 135