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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_host_model/] [rtl/] [verilog/] [tasks] - Blame information for rev 135

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  // Tasks
 
 
 
task automatic next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);
endtask // next
 
 
 
 
  // idle cycle
  task u_idle;
    begin
      addr  <= 24'h000000;
      wdata <= 16'h0000;
      rd    <= 1'b0;
      cs    <= 2'b00;
      wr    <= 1'b0;
      ub    <= 1'b0;
      lb    <= 1'b0;
      mask_rdata <= 16'h0000;
      next(1);
    end
  endtask
 
 
 
 
  // write cycle
  task u_write;
    input [23:0] a;
    input  [15:0] d;
 
    begin
 
      $display("%t %m cycle %x %x",$realtime,a,d );
 
      addr  <= a;
      wdata <= d;
      rd    <= 1'b0;
      cs    <= 2'b01;
      wr    <= 1'b1;
      ub    <= 1'b1;
      lb    <= 1'b1;
      next(4);
      rd    <= 1'b0;
      cs    <= 2'b00;
      wr    <= 1'b0;
      ub    <= 1'b0;
      lb    <= 1'b0;
      next(1);
 
    end
  endtask
 
  // read cycle
  task u_read;
    input   [23:0]  a;
    output  [15:0]   d;
 
     begin
 
      addr  <= a;
      wdata <= 16'h0000;
      rd    <= 1'b1;
      cs    <= 2'b01;
      wr    <= 1'b0;
      ub    <= 1'b1;
      lb    <= 1'b1;
 
      next(4);
 
      d     <= rdata;
      $display("%t %m  cycle %x %x",$realtime,a,rdata );
      rd    <= 1'b1;
      next(1);
      rd    <= 1'b0;
      ub    <= 1'b0;
      lb    <= 1'b0;
      cs    <= 2'b00;
      next(1);
    end
  endtask
 
  // Compare cycle (read data from location and compare with expected data)
  task u_cmp;
    input  [23:0] a;
    input  [15:0] d_exp;
 
     begin
      addr      <= a;
      wdata     <= 16'h0000;
      rd        <= 1'b1;
      ub        <= 1'b1;
      lb        <= 1'b1;
      cs        <= 2'b01;
      wr        <= 1'b0;
      exp_rdata <= d_exp;
 
      next(5);
      mask_rdata  <= 16'hffff;
 
 
      next(1);
      $display("%t %m   cycle %x %x",$realtime,a,d_exp );
      mask_rdata <= 16'h0000;
      rd         <= 1'b0;
      ub         <= 1'b0;
      lb         <= 1'b0;
      cs         <= 2'b00;
      next(1);
   end
  endtask
 

Line No.	Rev	Author	Line
1	135	jt_eaton	`// Tasks`
2
3
4
5			`task automatic next;`
6			`input [31:0] num;`
7			`repeat (num) @ (posedge clk);`
8			`endtask // next`
9
10
11
12
13			`// idle cycle`
14			`task u_idle;`
15			`begin`
16			`addr <= 24'h000000;`
17			`wdata <= 16'h0000;`
18			`rd <= 1'b0;`
19			`cs <= 2'b00;`
20			`wr <= 1'b0;`
21			`ub <= 1'b0;`
22			`lb <= 1'b0;`
23			`mask_rdata <= 16'h0000;`
24			`next(1);`
25			`end`
26			`endtask`
27
28
29
30
31			`// write cycle`
32			`task u_write;`
33			`input [23:0] a;`
34			`input [15:0] d;`
35
36			`begin`
37
38			`$display("%t %m cycle %x %x",$realtime,a,d );`
39
40			`addr <= a;`
41			`wdata <= d;`
42			`rd <= 1'b0;`
43			`cs <= 2'b01;`
44			`wr <= 1'b1;`
45			`ub <= 1'b1;`
46			`lb <= 1'b1;`
47			`next(4);`
48			`rd <= 1'b0;`
49			`cs <= 2'b00;`
50			`wr <= 1'b0;`
51			`ub <= 1'b0;`
52			`lb <= 1'b0;`
53			`next(1);`
54
55			`end`
56			`endtask`
57
58			`// read cycle`
59			`task u_read;`
60			`input [23:0] a;`
61			`output [15:0] d;`
62
63			`begin`
64
65			`addr <= a;`
66			`wdata <= 16'h0000;`
67			`rd <= 1'b1;`
68			`cs <= 2'b01;`
69			`wr <= 1'b0;`
70			`ub <= 1'b1;`
71			`lb <= 1'b1;`
72
73			`next(4);`
74
75			`d <= rdata;`
76			`$display("%t %m cycle %x %x",$realtime,a,rdata );`
77			`rd <= 1'b1;`
78			`next(1);`
79			`rd <= 1'b0;`
80			`ub <= 1'b0;`
81			`lb <= 1'b0;`
82			`cs <= 2'b00;`
83			`next(1);`
84			`end`
85			`endtask`
86
87			`// Compare cycle (read data from location and compare with expected data)`
88			`task u_cmp;`
89			`input [23:0] a;`
90			`input [15:0] d_exp;`
91
92			`begin`
93			`addr <= a;`
94			`wdata <= 16'h0000;`
95			`rd <= 1'b1;`
96			`ub <= 1'b1;`
97			`lb <= 1'b1;`
98			`cs <= 2'b01;`
99			`wr <= 1'b0;`
100			`exp_rdata <= d_exp;`
101
102			`next(5);`
103			`mask_rdata <= 16'hffff;`
104
105
106			`next(1);`
107			`$display("%t %m cycle %x %x",$realtime,a,d_exp );`
108			`mask_rdata <= 16'h0000;`
109			`rd <= 1'b0;`
110			`ub <= 1'b0;`
111			`lb <= 1'b0;`
112			`cs <= 2'b00;`
113			`next(1);`
114			`end`
115			`endtask`
116

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_host_model/] [rtl/] [verilog/] [tasks] - Blame information for rev 135