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module micro_bus16_model_def
#(parameter DELAY    = 15,
  parameter WIDTH    = 16
  )
 
 
 (
  input wire                  clk,
  input wire                  reset,
  input  wire [15:0]          rdata,
 
  output reg [23:0]           addr,
  output reg [15:0]           wdata,
  output reg [1:0]            cs,
  output reg                  rd,
  output reg                  wr,
  output reg                  ub,
  output reg                  lb
 
 
);
 
   reg [15:0]  exp_rdata;
   reg [15:0]  mask_rdata;
 
 
 
io_probe_in
 #(.MESG         ("micro rdata Error"),
   .WIDTH        (WIDTH),
   .IN_DELAY     (DELAY)
  )
rdata_tpb
  (
  .clk            (  clk        ),
  .expected_value (  exp_rdata  ),
  .mask           (  mask_rdata ),
  .signal         (  rdata      )
  );
 
 
 
 
 
 
 
 
 
 
 
 
 
always@(posedge clk)
  if(reset)
    begin
      addr  <= 24'h0000;
      wdata <=  16'h0000;
      wr    <=  1'b0;
      rd    <=  1'b0;
      cs    <=  2'b00;
      ub    <=  1'b0;
      lb    <=  1'b0;
      exp_rdata    <=  16'h0000;
      mask_rdata    <=  16'h0000;
   end
 
 
 
 
 
  // Tasks
 
 
 
task automatic next;
  input [31:0] num;
  repeat (num)       @ (posedge clk);
endtask // next
 
 
 
 
  // idle cycle
  task u_idle;
    begin
      addr  <= 24'h000000;
      wdata <= 16'h0000;
      rd    <= 1'b0;
      cs    <= 2'b00;
      wr    <= 1'b0;
      ub    <= 1'b0;
      lb    <= 1'b0;
      mask_rdata <= 16'h0000;
      next(1);
    end
  endtask
 
 
 
 
  // write cycle
  task u_write;
    input [23:0] a;
    input  [15:0] d;
 
    begin
 
      $display("%t %m cycle %x %x",$realtime,a,d );
 
      addr  <= a;
      wdata <= d;
      rd    <= 1'b0;
      cs    <= 2'b01;
      wr    <= 1'b1;
      ub    <= 1'b1;
      lb    <= 1'b1;
      next(4);
      rd    <= 1'b0;
      cs    <= 2'b00;
      wr    <= 1'b0;
      ub    <= 1'b0;
      lb    <= 1'b0;
      next(1);
 
    end
  endtask
 
  // read cycle
  task u_read;
    input   [23:0]  a;
    output  [15:0]   d;
 
     begin
 
      addr  <= a;
      wdata <= 16'h0000;
      rd    <= 1'b1;
      cs    <= 2'b01;
      wr    <= 1'b0;
      ub    <= 1'b1;
      lb    <= 1'b1;
 
      next(4);
 
      d     <= rdata;
      $display("%t %m  cycle %x %x",$realtime,a,rdata );
      rd    <= 1'b1;
      next(1);
      rd    <= 1'b0;
      ub    <= 1'b0;
      lb    <= 1'b0;
      cs    <= 2'b00;
      next(1);
    end
  endtask
 
  // Compare cycle (read data from location and compare with expected data)
  task u_cmp;
    input  [23:0] a;
    input  [15:0] d_exp;
 
     begin
      addr      <= a;
      wdata     <= 16'h0000;
      rd        <= 1'b1;
      ub        <= 1'b1;
      lb        <= 1'b1;
      cs        <= 2'b01;
      wr        <= 1'b0;
      exp_rdata <= d_exp;
 
      next(5);
      mask_rdata  <= 16'hffff;
 
 
      next(1);
      $display("%t %m   cycle %x %x",$realtime,a,d_exp );
      mask_rdata <= 16'h0000;
      rd         <= 1'b0;
      ub         <= 1'b0;
      lb         <= 1'b0;
      cs         <= 2'b00;
      next(1);
   end
  endtask
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	135	jt_eaton	`module micro_bus16_model_def`
2			`#(parameter DELAY = 15,`
3			`parameter WIDTH = 16`
4			`)`
5
6
7			`(`
8			`input wire clk,`
9			`input wire reset,`
10			`input wire [15:0] rdata,`
11
12			`output reg [23:0] addr,`
13			`output reg [15:0] wdata,`
14			`output reg [1:0] cs,`
15			`output reg rd,`
16			`output reg wr,`
17			`output reg ub,`
18			`output reg lb`
19
20
21			`);`
22
23			`reg [15:0] exp_rdata;`
24			`reg [15:0] mask_rdata;`
25
26
27
28			`io_probe_in`
29			`#(.MESG ("micro rdata Error"),`
30			`.WIDTH (WIDTH),`
31			`.IN_DELAY (DELAY)`
32			`)`
33			`rdata_tpb`
34			`(`
35			`.clk ( clk ),`
36			`.expected_value ( exp_rdata ),`
37			`.mask ( mask_rdata ),`
38			`.signal ( rdata )`
39			`);`
40
41
42
43
44
45
46
47
48
49
50
51
52
53			`always@(posedge clk)`
54			`if(reset)`
55			`begin`
56			`addr <= 24'h0000;`
57			`wdata <= 16'h0000;`
58			`wr <= 1'b0;`
59			`rd <= 1'b0;`
60			`cs <= 2'b00;`
61			`ub <= 1'b0;`
62			`lb <= 1'b0;`
63			`exp_rdata <= 16'h0000;`
64			`mask_rdata <= 16'h0000;`
65			`end`
66
67
68
69
70
71			`// Tasks`
72
73
74
75			`task automatic next;`
76			`input [31:0] num;`
77			`repeat (num) @ (posedge clk);`
78			`endtask // next`
79
80
81
82
83			`// idle cycle`
84			`task u_idle;`
85			`begin`
86			`addr <= 24'h000000;`
87			`wdata <= 16'h0000;`
88			`rd <= 1'b0;`
89			`cs <= 2'b00;`
90			`wr <= 1'b0;`
91			`ub <= 1'b0;`
92			`lb <= 1'b0;`
93			`mask_rdata <= 16'h0000;`
94			`next(1);`
95			`end`
96			`endtask`
97
98
99
100
101			`// write cycle`
102			`task u_write;`
103			`input [23:0] a;`
104			`input [15:0] d;`
105
106			`begin`
107
108			`$display("%t %m cycle %x %x",$realtime,a,d );`
109
110			`addr <= a;`
111			`wdata <= d;`
112			`rd <= 1'b0;`
113			`cs <= 2'b01;`
114			`wr <= 1'b1;`
115			`ub <= 1'b1;`
116			`lb <= 1'b1;`
117			`next(4);`
118			`rd <= 1'b0;`
119			`cs <= 2'b00;`
120			`wr <= 1'b0;`
121			`ub <= 1'b0;`
122			`lb <= 1'b0;`
123			`next(1);`
124
125			`end`
126			`endtask`
127
128			`// read cycle`
129			`task u_read;`
130			`input [23:0] a;`
131			`output [15:0] d;`
132
133			`begin`
134
135			`addr <= a;`
136			`wdata <= 16'h0000;`
137			`rd <= 1'b1;`
138			`cs <= 2'b01;`
139			`wr <= 1'b0;`
140			`ub <= 1'b1;`
141			`lb <= 1'b1;`
142
143			`next(4);`
144
145			`d <= rdata;`
146			`$display("%t %m cycle %x %x",$realtime,a,rdata );`
147			`rd <= 1'b1;`
148			`next(1);`
149			`rd <= 1'b0;`
150			`ub <= 1'b0;`
151			`lb <= 1'b0;`
152			`cs <= 2'b00;`
153			`next(1);`
154			`end`
155			`endtask`
156
157			`// Compare cycle (read data from location and compare with expected data)`
158			`task u_cmp;`
159			`input [23:0] a;`
160			`input [15:0] d_exp;`
161
162			`begin`
163			`addr <= a;`
164			`wdata <= 16'h0000;`
165			`rd <= 1'b1;`
166			`ub <= 1'b1;`
167			`lb <= 1'b1;`
168			`cs <= 2'b01;`
169			`wr <= 1'b0;`
170			`exp_rdata <= d_exp;`
171
172			`next(5);`
173			`mask_rdata <= 16'hffff;`
174
175
176			`next(1);`
177			`$display("%t %m cycle %x %x",$realtime,a,d_exp );`
178			`mask_rdata <= 16'h0000;`
179			`rd <= 1'b0;`
180			`ub <= 1'b0;`
181			`lb <= 1'b0;`
182			`cs <= 2'b00;`
183			`next(1);`
184			`end`
185			`endtask`
186
187
188
189
190
191			`endmodule`
192

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_host_model/] [rtl/] [verilog/] [top.sim] - Blame information for rev 135