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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_mem_model/] [rtl/] [verilog/] [logic] - Blame information for rev 135

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always@(posedge clk)
  if(reset)
    begin
      io_in_mem_ready           <=  1'b0;
      io_in_mem_valid           <=  1'b0;
      io_mem_backup_en          <=  1'b0;
      io_mem_req_cmd_ready           <=  1'b0;
      io_mem_req_data_ready          <=  1'b0;
      io_mem_resp_bits_data  <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;
      io_mem_resp_bits_tag   <= 5'b00000;
      io_mem_resp_ready          <=  1'b0;
      io_mem_resp_valid          <=  1'b0;
      io_out_mem_ready          <=  1'b0;
      io_out_mem_valid          <=  1'b0;
    end

Line No.	Rev	Author	Line
1	135	jt_eaton	`always@(posedge clk)`
2			`if(reset)`
3			`begin`
4			`io_in_mem_ready <= 1'b0;`
5			`io_in_mem_valid <= 1'b0;`
6			`io_mem_backup_en <= 1'b0;`
7			`io_mem_req_cmd_ready <= 1'b0;`
8			`io_mem_req_data_ready <= 1'b0;`
9			`io_mem_resp_bits_data <= 128'h0000_0000_0000_0000_0000_0000_0000_0000;`
10			`io_mem_resp_bits_tag <= 5'b00000;`
11			`io_mem_resp_ready <= 1'b0;`
12			`io_mem_resp_valid <= 1'b0;`
13			`io_out_mem_ready <= 1'b0;`
14			`io_out_mem_valid <= 1'b0;`
15			`end`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_mem_model/] [rtl/] [verilog/] [logic] - Blame information for rev 135