OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_mem_model/] [rtl/] [verilog/] [top.syn] - Blame information for rev 135

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 135 jt_eaton
module micro_bus16_model_def
2
#(parameter DELAY    = 15,
3
  parameter WIDTH    = 10
4
  )
5
 
6
 
7
 (
8
  input wire                  clk,
9
  input wire                  reset,
10
  input wire [15:0]           rdata,
11
 
12
  output reg [23:0]           addr,
13
  output reg [15:0]           wdata,
14
  output reg [1:0]            cs,
15
  output reg                  rd,
16
  output reg                  wr,
17
  output reg                  ub,
18
  output reg                  lb
19
 
20
 
21
 
22
);
23
 
24
 
25
   reg [15:0]  exp_rdata;
26
   reg [15:0]  mask_rdata;
27
 
28
 
29
 
30
 
31
io_probe_in
32
 #(.MESG         ("micro rdata Error"),
33
   .WIDTH        (16)
34
  )
35
rdata_tpb
36
  (
37
  .clk            (  clk        ),
38
  .expected_value (  exp_rdata  ),
39
  .mask           (  mask_rdata ),
40
  .signal         (  rdata      )
41
  );
42
 
43
 
44
always@(posedge clk)
45
  if(reset)
46
    begin
47
      addr  <=  24'h000000;
48
      wdata <=  16'h0000;
49
      wr    <=  1'b0;
50
      rd    <=  1'b0;
51
      cs    <=  2'b00;
52
      ub    <=  1'b0;
53
      lb    <=  1'b0;
54
      exp_rdata    <=  16'h0000;
55
      mask_rdata    <=  16'h0000;
56
   end
57
 
58
 
59
 
60
 
61
 
62
 
63
 
64
endmodule
65
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.