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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
io_probe
in
 

 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      io_probe_in
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      io_probe_in
    
  

 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
 
 
 
 

 
 
 
 
                
                        
                                verilog
                                verilog
                                io_probe_in
                                
                                        
                                                WIDTH
                                                8
                                        
 
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
 
  
 
 
 
                        
                                rtl
                                verilog:Kactus2:
                                verilog
                        
 
 
 
          
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

MESG" "
WIDTH1
IN_DELAY5

 

 
clk
wire
in

 
 
expected_value
wire
in
WIDTH-10

 
mask
wire
in
WIDTH-10

 
 
signal
wire
in
WIDTH-10

 
 
 
 

 

 
 
 
 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/io_probe_in
        verilogSourcemodule
      
 
 
      
        
        ../verilog/top.body.in
        verilogSourcefragment
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/io_probe_in
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [io_probe/] [rtl/] [xml/] [io_probe_in.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`io_probe`
40			`in`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44	135	jt_eaton
45			`gen_verilog_sim`
46			`104.0`
47			`none`
48			`:Simulation:`
49			`tools/verilog/gen_verilog`
50
51
52			`destination`
53			`io_probe_in`
54
55
56
57	131	jt_eaton
58	135	jt_eaton
59			`gen_verilog_syn`
60			`104.0`
61			`none`
62			`:Synthesis:`
63			`tools/verilog/gen_verilog`
64
65
66			`destination`
67			`io_probe_in`
68
69
70
71	131	jt_eaton
72
73	135	jt_eaton
74			`gen_verilogLib_sim`
75			`105.0`
76			`none`
77			`:Simulation:`
78			`tools/verilog/gen_verilogLib`
79
80
81			`dest_dir`
82			`../views`
83
84
85			`view`
86			`sim`
87
88
89
90	131	jt_eaton
91
92	135	jt_eaton
93			`gen_verilogLib_syn`
94			`105.0`
95			`none`
96			`:Synthesis:`
97			`tools/verilog/gen_verilogLib`
98
99
100			`dest_dir`
101			`../views`
102
103
104			`view`
105			`syn`
106
107
108
109	131	jt_eaton
110	135	jt_eaton
111	131	jt_eaton
112
113
114
115
116
117
118	135	jt_eaton
119	131	jt_eaton
120
121
122
123	135	jt_eaton
124
125			`verilog`
126			`verilog`
127			`io_probe_in`
128
129
130			`WIDTH`
131			`8`
132
133	131	jt_eaton
134	135	jt_eaton
135
136			`fs-sim`
137
138
139
140	131	jt_eaton
141	135	jt_eaton
142	131	jt_eaton
143
144	135	jt_eaton
145
146
147
148
149			`rtl`
150			`verilog:Kactus2:`
151			`verilog`
152
153
154
155
156
157			`verilog`
158
159
160			`ipxact:library="Testbench"`
161			`ipxact:name="toolflow"`
162			`ipxact:version="verilog"/>`
163
164
165
166
167
168
169
170
171
172			`sim:Simulation:`
173	131	jt_eaton
174	135	jt_eaton	`Verilog`
175
176
177			`fs-sim`
178
179
180	131	jt_eaton
181	135	jt_eaton
182			`syn:Synthesis:`
183	131	jt_eaton
184	135	jt_eaton	`Verilog`
185
186
187			`fs-syn`
188
189
190	131	jt_eaton
191
192	135	jt_eaton
193			`doc`
194
195
196			`ipxact:library="Testbench"`
197			`ipxact:name="toolflow"`
198			`ipxact:version="documentation"/>`
199
200			`:Documentation:`
201			`Verilog`
202
203	131	jt_eaton
204	135	jt_eaton
205	131	jt_eaton
206
207
208	135	jt_eaton
209			`MESG" "`
210			`WIDTH1`
211			`IN_DELAY5`
212
213	131	jt_eaton
214	135	jt_eaton
215	131	jt_eaton
216	135	jt_eaton	`clk`
217			`wire`
218			`in`
219
220	131	jt_eaton
221
222	135	jt_eaton	`expected_value`
223			`wire`
224			`in`
225			`WIDTH-10`
226
227	131	jt_eaton
228	135	jt_eaton	`mask`
229			`wire`
230			`in`
231			`WIDTH-10`
232
233	131	jt_eaton
234
235	135	jt_eaton	`signal`
236			`wire`
237			`in`
238			`WIDTH-10`
239
240	131	jt_eaton
241
242
243
244	135	jt_eaton
245	131	jt_eaton
246	135	jt_eaton
247	131	jt_eaton
248
249
250
251
252
253
254	135	jt_eaton
255	131	jt_eaton
256	135	jt_eaton
257			`fs-sim`
258	131	jt_eaton
259	135	jt_eaton
260
261			`../verilog/copyright`
262			`verilogSourceinclude`
263
264	134	jt_eaton
265	135	jt_eaton
266
267			`../verilog/sim/io_probe_in`
268			`verilogSourcemodule`
269
270	134	jt_eaton
271
272	135	jt_eaton
273
274			`../verilog/top.body.in`
275			`verilogSourcefragment`
276
277	134	jt_eaton
278	135	jt_eaton
279			`dest_dir../views/sim/`
280			`verilogSourcelibraryDir`
281
282	134	jt_eaton
283
284
285
286
287	135	jt_eaton
288	134	jt_eaton
289
290	135	jt_eaton
291			`fs-syn`
292	134	jt_eaton
293	135	jt_eaton
294
295			`../verilog/copyright`
296			`verilogSourceinclude`
297
298	134	jt_eaton
299	135	jt_eaton
300
301			`../verilog/syn/io_probe_in`
302			`verilogSourcemodule`
303
304	134	jt_eaton
305	135	jt_eaton
306			`dest_dir../views/syn/`
307			`verilogSourcelibraryDir`
308
309	134	jt_eaton
310
311
312
313	135	jt_eaton
314	134	jt_eaton
315
316
317
318
319	135	jt_eaton
320	134	jt_eaton
321
322
323
324
325
326	135	jt_eaton