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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [jtag_model/] [rtl/] [xml/] [jtag_model_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
jtag_model
def
 
 
 
 
 
 
 


  gen_verilog
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
  
    
      destination
      jtag_model_def
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 

 
 
 
  
 
 
 
 
    
      fs-sim
 
 
   
        
        ../verilog/jtag_model
        verilogSourcefragment
      
 
 
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
 
 
      
        
        ../verilog/sim/jtag_model_def
        verilogSourcemodule
      
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/sim/jtag_model_def
        verilogSourcemodule
      
 
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
 
 
 
 
  
 
 
 

       
 
            
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

DIVCNT4'h1
SIZE4

 

 
clk

wire
in

 
reset

wire
in

 
 
tclk

reg
out

 
trst_n

reg
out

 
tdo

reg
out

 
tms

reg
out

 
tdi

wire
in

 
 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [jtag_model/] [rtl/] [xml/] [jtag_model_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	134	jt_eaton
2	131	jt_eaton
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`jtag_model`
40			`def`
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49
50			`gen_verilog`
51			`104.0`
52			`none`
53			`:Simulation:`
54			`tools/verilog/gen_verilog`
55
56
57			`destination`
58			`jtag_model_def`
59
60
61
62	131	jt_eaton
63
64
65	134	jt_eaton
66	135	jt_eaton
67			`gen_verilogLib_sim`
68			`105.0`
69			`none`
70			`:Simulation:`
71			`tools/verilog/gen_verilogLib`
72
73
74			`dest_dir`
75			`../views`
76
77
78			`view`
79			`sim`
80
81
82
83	131	jt_eaton
84
85
86	135	jt_eaton
87			`gen_verilogLib_syn`
88			`105.0`
89			`none`
90			`:Synthesis:`
91			`tools/verilog/gen_verilogLib`
92
93
94			`dest_dir`
95			`../views`
96
97
98			`view`
99			`syn`
100
101
102
103	131	jt_eaton
104	135	jt_eaton
105	131	jt_eaton
106
107
108	135	jt_eaton
109	131	jt_eaton
110
111
112
113	135	jt_eaton
114			`fs-sim`
115	131	jt_eaton
116
117	135	jt_eaton
118
119			`../verilog/jtag_model`
120			`verilogSourcefragment`
121
122	134	jt_eaton
123	135	jt_eaton
124
125			`../verilog/copyright.v`
126			`verilogSourceinclude`
127
128	134	jt_eaton
129
130
131
132	135	jt_eaton
133
134			`../verilog/sim/jtag_model_def`
135			`verilogSourcemodule`
136
137	131	jt_eaton
138	135	jt_eaton
139			`dest_dir../views/sim/`
140			`verilogSourcelibraryDir`
141
142	131	jt_eaton
143
144
145	135	jt_eaton
146	131	jt_eaton
147
148
149
150
151
152
153	135	jt_eaton
154			`fs-syn`
155	131	jt_eaton
156	135	jt_eaton
157
158			`../verilog/sim/jtag_model_def`
159			`verilogSourcemodule`
160
161	131	jt_eaton
162
163	135	jt_eaton
164			`dest_dir../views/syn/`
165			`verilogSourcelibraryDir`
166
167	131	jt_eaton
168
169	135	jt_eaton
170	131	jt_eaton
171
172
173
174
175
176
177	135	jt_eaton
178	131	jt_eaton
179
180
181	135	jt_eaton
182
183	131	jt_eaton
184	135	jt_eaton
185			`verilog`
186
187
188			`ipxact:library="Testbench"`
189			`ipxact:name="toolflow"`
190			`ipxact:version="verilog"/>`
191
192
193	131	jt_eaton
194
195	134	jt_eaton
196
197
198
199	135	jt_eaton
200			`sim:Simulation:`
201			`Verilog`
202
203
204			`fs-sim`
205
206
207	131	jt_eaton
208
209	135	jt_eaton
210			`syn:Synthesis:`
211			`Verilog`
212
213
214			`fs-syn`
215
216
217	131	jt_eaton
218
219	135	jt_eaton
220			`doc`
221
222
223			`ipxact:library="Testbench"`
224			`ipxact:name="toolflow"`
225			`ipxact:version="documentation"/>`
226
227			`:Documentation:`
228			`Verilog`
229
230	131	jt_eaton
231	135	jt_eaton
232	131	jt_eaton
233
234
235	135	jt_eaton
236			`DIVCNT4'h1`
237			`SIZE4`
238
239	131	jt_eaton
240	135	jt_eaton
241	131	jt_eaton
242	135	jt_eaton	`clk`
243
244			`wire`
245			`in`
246
247	131	jt_eaton
248	135	jt_eaton	`reset`
249
250			`wire`
251			`in`
252
253	131	jt_eaton
254
255	135	jt_eaton	`tclk`
256
257			`reg`
258			`out`
259
260	131	jt_eaton
261	135	jt_eaton	`trst_n`
262
263			`reg`
264			`out`
265
266	131	jt_eaton
267	135	jt_eaton	`tdo`
268
269			`reg`
270			`out`
271
272	131	jt_eaton
273	135	jt_eaton	`tms`
274
275			`reg`
276			`out`
277
278	131	jt_eaton
279	135	jt_eaton	`tdi`
280
281			`wire`
282			`in`
283
284	131	jt_eaton
285
286	135	jt_eaton
287	131	jt_eaton
288	135	jt_eaton
289	131	jt_eaton
290
291
292
293
294	135	jt_eaton