Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

Testbench

micro_bus16_model

def

  gen_verilog_sim

  105.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      micro_bus16_model_def

  gen_verilog_syn

  105.0

  none

  :*Synthesis:*

  tools/verilog/gen_verilog

      destination

      micro_bus16_model_def

                                Hierarchical

              Hierarchical

                     Hierarchical

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

DELAY15

WIDTH16

clk

wire

in

reset

wire

in

addr

reg

out

230

wdata

reg

out

150

rd

reg

out

wr

reg

out

lb

reg

out

ub

reg

out

rdata

wire

in

150

cs

reg

out

10

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/logic

        verilogSourcefragment

        ../verilog/tasks

        verilogSourcefragment

        ../verilog/sim/micro_bus16_model_def

        verilogSourcemodule

        dest_dir../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/logic

        verilogSourcefragment

        ../verilog/syn/micro_bus16_model_def

        verilogSourcemodule

        dest_dir../views/syn/

        verilogSourcelibraryDir