Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

Testbench

mt45w8mw12

def

  gen_verilog_sim

  104.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      mt45w8mw12_def

  gen_verilog_syn

  104.0

  none

  :*Synthesis:*

  tools/verilog/gen_verilog

      destination

      mt45w8mw12_def

                                verilog

                                verilog

                                mt45w8mw12_def

                                                ADDR_BITS

                                                23

                                                DQ_BITS

                                                16

                                        fs-sim

                                rtl

                                verilog:Kactus2:

                                verilog

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

ADDR_BITS23

DQ_BITS16

MEM_BITS16

clk

wire

in

adv_n

wire

in

cre

wire

in

o_wait

wire

out

ce_n

wire

in

oe_n

wire

in

we_n

wire

in

lb_n

wire

in

ub_n

wire

in

addr

wire

in

ADDR_BITS-10

dq

wire

inout

DQ_BITS-10

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/top.sim

        verilogSourcefragment

        ../verilog/sim/mt45w8mw12_def

        verilogSourcemodule

        dest_dir../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/top.syn

        verilogSourcefragment

        ../verilog/syn/mt45w8mw12_def

        verilogSourcemodule

        dest_dir../views/syn/

        verilogSourcelibraryDir