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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_host/] [rtl/] [xml/] [spi_host_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
spi_host
def
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
  
    
      destination
      spi_host_def
    
  

 
 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
  
    
      destination
      spi_host_def
    
  

 
 
 

 
 
 
 
 
 

 
        
                        
                                Hierarchical
                                
                        
                
 
 
 
 
 
  
 
 
             
              Hierarchical
                  Hierarchical
              
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 

 
clk
wire
in

 
reset
wire
in

 
 
busy
wire
in

 
rx_read
wire
in

 
 
rx_full
wire
in

 
rx_parity_error
wire
in

 
rx_parity_rcv
wire
in

 
rx_parity_cal
wire
in

 
tx_ack_error
wire
in

 
rx_frame_error
wire
in

 
rx_clr
reg
out

 
tx_write
reg
out

 
 

tx_data
reg
out70

 
 

rx_data
wire
in70

 
 

 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/logic
        verilogSourcefragment
      
 
      
        
        ../verilog/tasks
        verilogSourcefragment
      
 
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/spi_host_def
        verilogSourcemodule
      
 
 
      
        dest_dir../views/sim/
        verilogSourcelibraryDir
      
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/logic
        verilogSourcefragment
      
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/spi_host_def
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
 
    
 
 
 
  
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_host/] [rtl/] [xml/] [spi_host_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`spi_host`
40			`def`
41
42
43
44
45
46
47
48			`gen_verilog_sim`
49			`104.0`
50			`none`
51			`:Simulation:`
52			`tools/verilog/gen_verilog`
53
54
55			`destination`
56			`spi_host_def`
57
58
59
60
61
62
63
64			`gen_verilog_syn`
65			`104.0`
66			`none`
67			`:Synthesis:`
68			`tools/verilog/gen_verilog`
69
70
71			`destination`
72			`spi_host_def`
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90			`Hierarchical`
91
92
93
94
95
96
97
98
99
100
101
102
103			`Hierarchical`
104			`Hierarchical`
105
106
107
108
109			`verilog`
110
111
112			`ipxact:library="Testbench"`
113			`ipxact:name="toolflow"`
114			`ipxact:version="verilog"/>`
115
116
117
118
119
120
121
122
123
124			`sim:Simulation:`
125			`Verilog`
126
127
128			`fs-sim`
129
130
131
132
133			`syn:Synthesis:`
134			`Verilog`
135
136
137			`fs-syn`
138
139
140
141
142
143			`doc`
144
145
146			`ipxact:library="Testbench"`
147			`ipxact:name="toolflow"`
148			`ipxact:version="documentation"/>`
149
150			`:Documentation:`
151			`Verilog`
152
153
154
155
156
157
158
159			`clk`
160			`wire`
161			`in`
162
163
164			`reset`
165			`wire`
166			`in`
167
168
169
170			`busy`
171			`wire`
172			`in`
173
174
175			`rx_read`
176			`wire`
177			`in`
178
179
180
181			`rx_full`
182			`wire`
183			`in`
184
185
186			`rx_parity_error`
187			`wire`
188			`in`
189
190
191			`rx_parity_rcv`
192			`wire`
193			`in`
194
195
196			`rx_parity_cal`
197			`wire`
198			`in`
199
200
201			`tx_ack_error`
202			`wire`
203			`in`
204
205
206			`rx_frame_error`
207			`wire`
208			`in`
209
210
211			`rx_clr`
212			`reg`
213			`out`
214
215
216			`tx_write`
217			`reg`
218			`out`
219
220
221
222
223			`tx_data`
224			`reg`
225			`out70`
226
227
228
229
230			`rx_data`
231			`wire`
232			`in70`
233
234
235
236
237
238
239
240
241
242
243
244			`fs-sim`
245
246
247
248			`../verilog/logic`
249			`verilogSourcefragment`
250
251
252
253
254			`../verilog/tasks`
255			`verilogSourcefragment`
256
257
258
259
260
261			`../verilog/copyright`
262			`verilogSourceinclude`
263
264
265
266
267			`../verilog/sim/spi_host_def`
268			`verilogSourcemodule`
269
270
271
272
273			`dest_dir../views/sim/`
274			`verilogSourcelibraryDir`
275
276
277
278
279
280
281			`fs-syn`
282
283
284
285			`../verilog/logic`
286			`verilogSourcefragment`
287
288
289
290
291			`../verilog/copyright`
292			`verilogSourceinclude`
293
294
295
296
297			`../verilog/syn/spi_host_def`
298			`verilogSourcemodule`
299
300
301
302			`dest_dir../views/syn/`
303			`verilogSourcelibraryDir`
304
305
306
307
308
309
310
311
312
313
314
315
316