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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_model/] [rtl/] [verilog/] [top.master.rtl] - Blame information for rev 135

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reg [31:0]     TX_Data;
reg            START;
 
reg            spi_clk_roll;
reg            spi_clk_m;
reg [SIZE-1:0] spi_clk_cnt;
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
  if(reset)  spi_clk_roll <= 1'b0;
  else
   begin
   spi_clk_roll <= (spi_clk_cnt == CLKCNT);
   end
  end
 
 
 
always @(posedge clk  or posedge reset )
  begin
 
  if(reset)           spi_clk_cnt <= 8'h00;
  else
  begin
   if (spi_clk_roll)  spi_clk_cnt <= 0;
   else               spi_clk_cnt <= spi_clk_cnt + 1;
  end
  end
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
  if(reset)  spi_clk_m <= 1'b0;
  else
   begin
   spi_clk_m           <=  spi_clk_roll ^ spi_clk_m ;
   end
  end
 
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
  if(reset)  spi_clk <= 1'b0;
  else
  if(spi_sel_n)  spi_clk <= 1'b0;
  else
   begin
   spi_clk           <=  spi_clk_roll ^ spi_clk_m ;
   end
  end
 
 
 
 
 
 
 
 
 
reg [5:0]  bit_cnt;
 
 
always @(posedge clk  or posedge reset )
  begin
   if(reset)  bit_cnt <= 6'b000000;
   else
   if(!START) bit_cnt <= 6'b000000;
   else
 
 begin
    if(spi_clk_roll && spi_clk_m  )
    begin
    if( bit_cnt == 6'b100001)     bit_cnt  <= 6'b000000;
    else                          bit_cnt  <= bit_cnt + 6'b000001;
    end
   end
 
 
 
end
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
 
  if(reset)  spi_sel_n <= 1'b1;
  else
  begin
   if (START && spi_clk_m && spi_clk_roll )  spi_sel_n <= 1'b0;
   else if ( bit_cnt == 6'b100001)           spi_sel_n <= 1'b1;
   else  spi_sel_n <= spi_sel_n;
  end
  end
 
 
 
always @(posedge clk  )
 
  begin
   if ((!spi_sel_n)  && spi_clk_m && spi_clk_roll )  TX_Data  <= {TX_Data[30:0],1'b0};
   else TX_Data                                               <= TX_Data;
  end
 
 
 
 
 
 
always @(posedge clk  or posedge reset )
  begin
   if(reset)  spi_mosi <= 1'b0;
   else       spi_mosi <= TX_Data[31];
  end
 
 
 
always @(posedge clk  )
 
  begin
   if ((!spi_sel_n)  && (!spi_clk_m) && spi_clk_roll )
            RX_Data           <=   {RX_Data[30:0],spi_miso};
   else     RX_Data           <=    RX_Data;
  end
 
 
 
always @(posedge clk  or posedge reset )
  begin
   if(reset)  START <= 1'b0;
   else
    begin
    if(spi_clk_roll && spi_clk_m  )
    begin
    if( bit_cnt == 6'b100000)     START  <= 1'b0;
    else                          START  <= START;
    end
   end
   end
 
 
wire mask;
 
assign  mask         = ( bit_cnt == 6'b100001);
assign  mask_rx_data = {32{mask}};

Line No.	Rev	Author	Line
1	135	jt_eaton
2			`reg [31:0] TX_Data;`
3			`reg START;`
4
5			`reg spi_clk_roll;`
6			`reg spi_clk_m;`
7			`reg [SIZE-1:0] spi_clk_cnt;`
8
9
10
11
12			`always @(posedge clk or posedge reset )`
13			`begin`
14			`if(reset) spi_clk_roll <= 1'b0;`
15			`else`
16			`begin`
17			`spi_clk_roll <= (spi_clk_cnt == CLKCNT);`
18			`end`
19			`end`
20
21
22
23			`always @(posedge clk or posedge reset )`
24			`begin`
25
26			`if(reset) spi_clk_cnt <= 8'h00;`
27			`else`
28			`begin`
29			`if (spi_clk_roll) spi_clk_cnt <= 0;`
30			`else spi_clk_cnt <= spi_clk_cnt + 1;`
31			`end`
32			`end`
33
34
35
36
37			`always @(posedge clk or posedge reset )`
38			`begin`
39			`if(reset) spi_clk_m <= 1'b0;`
40			`else`
41			`begin`
42			`spi_clk_m <= spi_clk_roll ^ spi_clk_m ;`
43			`end`
44			`end`
45
46
47
48
49
50			`always @(posedge clk or posedge reset )`
51			`begin`
52			`if(reset) spi_clk <= 1'b0;`
53			`else`
54			`if(spi_sel_n) spi_clk <= 1'b0;`
55			`else`
56			`begin`
57			`spi_clk <= spi_clk_roll ^ spi_clk_m ;`
58			`end`
59			`end`
60
61
62
63
64
65
66
67
68
69			`reg [5:0] bit_cnt;`
70
71
72			`always @(posedge clk or posedge reset )`
73			`begin`
74			`if(reset) bit_cnt <= 6'b000000;`
75			`else`
76			`if(!START) bit_cnt <= 6'b000000;`
77			`else`
78
79			`begin`
80			`if(spi_clk_roll && spi_clk_m )`
81			`begin`
82			`if( bit_cnt == 6'b100001) bit_cnt <= 6'b000000;`
83			`else bit_cnt <= bit_cnt + 6'b000001;`
84			`end`
85			`end`
86
87
88
89			`end`
90
91
92
93
94			`always @(posedge clk or posedge reset )`
95			`begin`
96
97			`if(reset) spi_sel_n <= 1'b1;`
98			`else`
99			`begin`
100			`if (START && spi_clk_m && spi_clk_roll ) spi_sel_n <= 1'b0;`
101			`else if ( bit_cnt == 6'b100001) spi_sel_n <= 1'b1;`
102			`else spi_sel_n <= spi_sel_n;`
103			`end`
104			`end`
105
106
107
108			`always @(posedge clk )`
109
110			`begin`
111			`if ((!spi_sel_n) && spi_clk_m && spi_clk_roll ) TX_Data <= {TX_Data[30:0],1'b0};`
112			`else TX_Data <= TX_Data;`
113			`end`
114
115
116
117
118
119
120			`always @(posedge clk or posedge reset )`
121			`begin`
122			`if(reset) spi_mosi <= 1'b0;`
123			`else spi_mosi <= TX_Data[31];`
124			`end`
125
126
127
128			`always @(posedge clk )`
129
130			`begin`
131			`if ((!spi_sel_n) && (!spi_clk_m) && spi_clk_roll )`
132			`RX_Data <= {RX_Data[30:0],spi_miso};`
133			`else RX_Data <= RX_Data;`
134			`end`
135
136
137
138			`always @(posedge clk or posedge reset )`
139			`begin`
140			`if(reset) START <= 1'b0;`
141			`else`
142			`begin`
143			`if(spi_clk_roll && spi_clk_m )`
144			`begin`
145			`if( bit_cnt == 6'b100000) START <= 1'b0;`
146			`else START <= START;`
147			`end`
148			`end`
149			`end`
150
151
152			`wire mask;`
153
154			`assign mask = ( bit_cnt == 6'b100001);`
155			`assign mask_rx_data = {32{mask}};`

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [spi_model/] [rtl/] [verilog/] [top.master.rtl] - Blame information for rev 135