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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sch/] [axi_model_slave.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 1800 300 1 0 0 in_port_vector.sym
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{
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T 1800 300 5 10 1 1 0 6 1 1
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refdes=axi_wstrb[3:0]
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}
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C 1800 700 1 0 0 in_port_vector.sym
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{
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T 1800 700 5 10 1 1 0 6 1 1
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refdes=axi_wdata[31:0]
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}
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C 1800 1100 1 0 0 in_port_vector.sym
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{
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T 1800 1100 5 10 1 1 0 6 1 1
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refdes=axi_awsize[2:0]
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}
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C 1800 1500 1 0 0 in_port_vector.sym
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{
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T 1800 1500 5 10 1 1 0 6 1 1
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refdes=axi_awlen[7:0]
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}
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C 1800 1900 1 0 0 in_port_vector.sym
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{
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T 1800 1900 5 10 1 1 0 6 1 1
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refdes=axi_awid[11:0]
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}
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C 1800 2300 1 0 0 in_port_vector.sym
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{
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T 1800 2300 5 10 1 1 0 6 1 1
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refdes=axi_awburst[1:0]
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}
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C 1800 2700 1 0 0 in_port_vector.sym
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{
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T 1800 2700 5 10 1 1 0 6 1 1
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refdes=axi_awaddr[31:0]
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}
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C 1800 3100 1 0 0 in_port_vector.sym
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{
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T 1800 3100 5 10 1 1 0 6 1 1
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refdes=axi_arsize[2:0]
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}
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C 1800 3500 1 0 0 in_port_vector.sym
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{
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T 1800 3500 5 10 1 1 0 6 1 1
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refdes=axi_arlen[7:0]
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}
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C 1800 3900 1 0 0 in_port_vector.sym
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{
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T 1800 3900 5 10 1 1 0 6 1 1
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refdes=axi_arid[11:0]
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}
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C 1800 4300 1 0 0 in_port_vector.sym
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{
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T 1800 4300 5 10 1 1 0 6 1 1
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refdes=axi_arburst[1:0]
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}
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C 1800 4700 1 0 0 in_port_vector.sym
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{
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T 1800 4700 5 10 1 1 0 6 1 1
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refdes=axi_araddr[31:0]
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}
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C 1800 5100 1 0 0 in_port.sym
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{
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T 1800 5100 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 1800 5500 1 0 0 in_port.sym
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{
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T 1800 5500 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 1800 5900 1 0 0 in_port.sym
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{
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T 1800 5900 5 10 1 1 0 6 1 1
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refdes=axi_wvalid
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}
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C 1800 6300 1 0 0 in_port.sym
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{
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T 1800 6300 5 10 1 1 0 6 1 1
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refdes=axi_wlast
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}
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C 1800 6700 1 0 0 in_port.sym
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{
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T 1800 6700 5 10 1 1 0 6 1 1
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refdes=axi_rready
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}
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C 1800 7100 1 0 0 in_port.sym
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{
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T 1800 7100 5 10 1 1 0 6 1 1
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refdes=axi_bready
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}
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C 1800 7500 1 0 0 in_port.sym
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{
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T 1800 7500 5 10 1 1 0 6 1 1
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refdes=axi_awvalid
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}
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C 1800 7900 1 0 0 in_port.sym
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{
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T 1800 7900 5 10 1 1 0 6 1 1
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refdes=axi_arvalid
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}
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C 4600 300  1 0  0 out_port_vector.sym
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{
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T 5600 300 5  10 1 1 0 0 1 1
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refdes=axi_rid[11:0]
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}
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C 4600 700  1 0  0 out_port_vector.sym
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{
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T 5600 700 5  10 1 1 0 0 1 1
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refdes=axi_rdata[31:0]
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}
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C 4600 1100  1 0  0 out_port_vector.sym
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{
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T 5600 1100 5  10 1 1 0 0 1 1
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refdes=axi_bresp[1:0]
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}
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C 4600 1500  1 0  0 out_port_vector.sym
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{
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T 5600 1500 5  10 1 1 0 0 1 1
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refdes=axi_bid[11:0]
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}
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C 4600 1900  1 0 0 out_port.sym
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{
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T 5600 1900 5  10 1 1 0 0 1 1
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refdes=axi_wready
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}
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C 4600 2300  1 0 0 out_port.sym
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{
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T 5600 2300 5  10 1 1 0 0 1 1
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refdes=axi_rvalid
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}
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C 4600 2700  1 0 0 out_port.sym
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{
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T 5600 2700 5  10 1 1 0 0 1 1
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refdes=axi_rlast
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}
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C 4600 3100  1 0 0 out_port.sym
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{
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T 5600 3100 5  10 1 1 0 0 1 1
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refdes=axi_bvalid
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}
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C 4600 3500  1 0 0 out_port.sym
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{
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T 5600 3500 5  10 1 1 0 0 1 1
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refdes=axi_awready
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}
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C 4600 3900  1 0 0 out_port.sym
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{
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T 5600 3900 5  10 1 1 0 0 1 1
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refdes=axi_arready
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}

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