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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sch/] [uart_host_def.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 1900 300 1 0 0 in_port_vector.sym
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{
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T 1900 300 5 10 1 1 0 6 1 1
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refdes=rxd_data_out[7:0]
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}
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C 1900 700 1 0 0 in_port.sym
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{
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T 1900 700 5 10 1 1 0 6 1 1
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refdes=txd_buffer_empty
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}
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C 1900 1100 1 0 0 in_port.sym
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{
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T 1900 1100 5 10 1 1 0 6 1 1
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refdes=rxd_stop_error
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}
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C 1900 1500 1 0 0 in_port.sym
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{
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T 1900 1500 5 10 1 1 0 6 1 1
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refdes=rxd_parity_error
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}
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C 1900 1900 1 0 0 in_port.sym
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{
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T 1900 1900 5 10 1 1 0 6 1 1
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refdes=rxd_data_avail
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}
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C 1900 2300 1 0 0 in_port.sym
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{
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T 1900 2300 5 10 1 1 0 6 1 1
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refdes=reset
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}
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C 1900 2700 1 0 0 in_port.sym
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{
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T 1900 2700 5 10 1 1 0 6 1 1
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refdes=clk
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}
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C 5000 300  1 0  0 out_port_vector.sym
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{
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T 6000 300 5  10 1 1 0 0 1 1
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refdes=txd_data_in[7:0]
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}
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C 5000 700  1 0 0 out_port.sym
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{
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T 6000 700 5  10 1 1 0 0 1 1
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refdes=txd_parity
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}
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C 5000 1100  1 0 0 out_port.sym
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{
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T 6000 1100 5  10 1 1 0 0 1 1
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refdes=txd_load
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}
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C 5000 1500  1 0 0 out_port.sym
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{
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T 6000 1500 5  10 1 1 0 0 1 1
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refdes=txd_force_parity
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}
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C 5000 1900  1 0 0 out_port.sym
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{
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T 6000 1900 5  10 1 1 0 0 1 1
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refdes=txd_break
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}
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C 5000 2300  1 0 0 out_port.sym
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{
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T 6000 2300 5  10 1 1 0 0 1 1
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refdes=rxd_parity
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}
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C 5000 2700  1 0 0 out_port.sym
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{
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T 6000 2700 5  10 1 1 0 0 1 1
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refdes=rxd_force_parity
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}
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C 5000 3100  1 0 0 out_port.sym
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{
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T 6000 3100 5  10 1 1 0 0 1 1
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refdes=rxd_data_avail_stb
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}
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C 5000 3500  1 0 0 out_port.sym
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{
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T 6000 3500 5  10 1 1 0 0 1 1
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refdes=parity_enable
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}

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