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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [ara.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
toolflow
ara
 

 
 
 
 

  gen_ara_filelist
  104.0
  none
  
    :*Synthesis:*
  
  tools/sys/gen_child_filelist
  
    
      top
    
    
      suffix
      ARA
    
    
      leader
      "read_verilog  "
    
    
      overlay_src_ven
      opencores.org
    
    
      overlay_src_lib
      cde
    
    
      overlay_des_ven
      lattice.com
    
    
      overlay_des_lib
      iceskate
    
 
  

 
 
 
 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      view
      syn
    
  

 

 

 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 

 
 

 
       
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
      
 

 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36
37			`opencores.org`
38			`Testbench`
39			`toolflow`
40			`ara`
41
42
43
44
45
46
47
48			`gen_ara_filelist`
49			`104.0`
50			`none`
51
52			`:Synthesis:`
53
54			`tools/sys/gen_child_filelist`
55
56
57			`top`
58
59
60			`suffix`
61			`ARA`
62
63
64			`leader`
65			`"read_verilog "`
66
67
68			`overlay_src_ven`
69			`opencores.org`
70
71
72			`overlay_src_lib`
73			`cde`
74
75
76			`overlay_des_ven`
77			`lattice.com`
78
79
80			`overlay_des_lib`
81			`iceskate`
82
83
84
85
86
87
88
89
90
91
92
93			`gen_verilogLib_syn`
94			`105.0`
95			`none`
96			`:Synthesis:`
97			`tools/verilog/gen_verilogLib`
98
99
100			`view`
101			`syn`
102
103
104
105
106
107
108
109
110
111			`fs-syn`
112
113
114			`dest_dir`
115			`../views/syn/`
116			`verilogSource`
117			`libraryDir`
118
119
120
121
122
123
124
125
126
127
128
129			`syn`
130			`:Synthesis:`
131			`Verilog`
132
133			`fs-syn`
134
135
136
137
138
139
140
141
142
143
144
145

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [ara.xml] - Blame information for rev 135