URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilator.xml] - Blame information for rev 135

Details | Compare with Previous | View Log





xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
toolflow
verilator
 

 
 

  gen_filelists
  104.0
  none
  
    :*Synthesis:*
  
  tools/sys/gen_child_filelist
    
    
      top_file
      "./TestBench"
    
    
      top
    
  

 
 

  gen_cov_filelist
  104.0
  none
  
    :*Lint:*
  
  tools/sys/gen_child_filelist
  
    
      top_file
      "-v ./TestBench"
    
    
      top
    
    
      suffix
      COV
    
    
      leader
      "-v "
    
  

 
 
 
 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      view
      syn
    
  

 
 
 

  gen_verilogLib_lint
  105.0
  none
  :*Lint:*
  tools/verilog/gen_verilogLib
    
    
      view
      lint
    
  

 
 
 
 
 
 
 

 
 
 

 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/lint/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
 
 

 
 
 
 
 
 
 
 
 

 
      
        PERIOD40
        TIMEOUT100000
      
 
                
                        
                                Bfm
                                
                        
                
 
 
 
 
 
    
 
              
              Bfm
              Bfm
 
              
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
 
 
 
 
    
 
 
 
    
 
      clk
        wire
        in
      
 
      START
        wire
        in
      
 
 
      FAIL
        reg
        out
      
 
 
      FINISH
        reg
        out
      
 
    
 
 

 
 
 

 
 
 
 
 
 

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilator.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`toolflow`
40			`verilator`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44
45	135	jt_eaton
46			`gen_filelists`
47			`104.0`
48			`none`
49
50	131	jt_eaton	`:Synthesis:`
51	135	jt_eaton
52			`tools/sys/gen_child_filelist`
53
54
55			`top_file`
56			`"./TestBench"`
57
58
59			`top`
60
61
62
63	131	jt_eaton
64
65	135	jt_eaton
66			`gen_cov_filelist`
67			`104.0`
68			`none`
69
70	131	jt_eaton	`:Lint:`
71	135	jt_eaton
72			`tools/sys/gen_child_filelist`
73
74
75			`top_file`
76			`"-v ./TestBench"`
77
78
79			`top`
80
81
82			`suffix`
83			`COV`
84
85
86			`leader`
87			`"-v "`
88
89
90
91	131	jt_eaton
92
93
94
95
96
97	135	jt_eaton
98			`gen_verilogLib_syn`
99			`105.0`
100			`none`
101			`:Synthesis:`
102			`tools/verilog/gen_verilogLib`
103
104
105			`view`
106			`syn`
107
108
109
110	131	jt_eaton
111
112
113	135	jt_eaton
114			`gen_verilogLib_lint`
115			`105.0`
116			`none`
117			`:Lint:`
118			`tools/verilog/gen_verilogLib`
119
120
121			`view`
122			`lint`
123
124
125
126	131	jt_eaton
127
128
129
130
131
132
133	135	jt_eaton
134	131	jt_eaton
135
136
137	135	jt_eaton
138	131	jt_eaton
139
140	135	jt_eaton
141			`fs-syn`
142	131	jt_eaton
143	135	jt_eaton
144			`dest_dir`
145			`../views/syn/`
146			`verilogSource`
147			`libraryDir`
148
149	131	jt_eaton
150	135	jt_eaton
151	131	jt_eaton
152
153	135	jt_eaton
154			`fs-lint`
155	131	jt_eaton
156	135	jt_eaton
157			`dest_dir`
158			`../views/lint/`
159			`verilogSource`
160			`libraryDir`
161
162	131	jt_eaton
163	135	jt_eaton
164	131	jt_eaton
165
166
167
168
169
170	135	jt_eaton
171	131	jt_eaton
172
173
174
175
176
177
178
179
180	135	jt_eaton
181	131	jt_eaton
182	135	jt_eaton
183			`PERIOD40`
184			`TIMEOUT100000`
185
186	131	jt_eaton
187	135	jt_eaton
188
189			`Bfm`
190
191
192
193	131	jt_eaton
194
195
196
197	135	jt_eaton
198
199	131	jt_eaton
200	135	jt_eaton
201			`Bfm`
202			`Bfm`
203	131	jt_eaton
204	135	jt_eaton
205	131	jt_eaton
206
207	135	jt_eaton
208			`syn`
209			`:Synthesis:`
210			`Verilog`
211
212			`fs-syn`
213
214	131	jt_eaton
215
216
217	135	jt_eaton
218			`lint`
219			`:Lint:`
220			`Verilog`
221
222			`fs-lint`
223
224	131	jt_eaton
225
226
227
228
229	135	jt_eaton
230	131	jt_eaton
231
232
233	135	jt_eaton
234	131	jt_eaton
235	135	jt_eaton	`clk`
236			`wire`
237			`in`
238
239	131	jt_eaton
240	135	jt_eaton	`START`
241			`wire`
242			`in`
243
244	131	jt_eaton
245
246	135	jt_eaton	`FAIL`
247			`reg`
248			`out`
249
250	131	jt_eaton
251
252	135	jt_eaton	`FINISH`
253			`reg`
254			`out`
255
256	131	jt_eaton
257	135	jt_eaton
258	131	jt_eaton
259
260	135	jt_eaton
261	131	jt_eaton
262	135	jt_eaton
263
264
265
266
267
268	131	jt_eaton
269
270