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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilog.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
Testbench
toolflow
verilog
 

 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      view
      syn
    
  

 
 
 
 
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
   
      fs-sim
 
      
        dest_dir
        ../views/sim/
        verilogSource
        libraryDir
      
 
   
 
 
 
   
      fs-syn
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
   
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSource
        libraryDir
      
 
   
 
 
 
 
 
 

 
 
 
 
 
 

 
 
 
 
       
 
 
 
 
              
              sim
              :*Simulation:*
              Verilog
              
              fs-sim
              
 
 
              
              syn
              :*Synthesis:*
              Verilog
              
              fs-syn
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              
              fs-lint
              
 
 
 
 
 
 
 
 
      
 
 
 

 

 
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`Testbench`
39			`toolflow`
40			`verilog`
41	131	jt_eaton
42	135	jt_eaton
43	131	jt_eaton
44
45	135	jt_eaton
46			`gen_verilogLib_sim`
47			`105.0`
48			`none`
49			`:Simulation:`
50			`tools/verilog/gen_verilogLib`
51
52
53			`view`
54			`sim`
55
56
57
58	131	jt_eaton
59
60
61	135	jt_eaton
62			`gen_verilogLib_syn`
63			`105.0`
64			`none`
65			`:Synthesis:`
66			`tools/verilog/gen_verilogLib`
67
68
69			`view`
70			`syn`
71
72
73
74	131	jt_eaton
75
76
77
78
79
80
81
82
83
84
85
86	135	jt_eaton
87	131	jt_eaton
88
89
90	135	jt_eaton
91	131	jt_eaton
92
93
94
95
96	135	jt_eaton
97			`fs-sim`
98	131	jt_eaton
99	135	jt_eaton
100			`dest_dir`
101			`../views/sim/`
102			`verilogSource`
103			`libraryDir`
104
105	131	jt_eaton
106	135	jt_eaton
107	131	jt_eaton
108
109
110	135	jt_eaton
111			`fs-syn`
112	131	jt_eaton
113	135	jt_eaton
114			`dest_dir`
115			`../views/syn/`
116			`verilogSource`
117			`libraryDir`
118
119	131	jt_eaton
120	135	jt_eaton
121	131	jt_eaton
122
123	135	jt_eaton
124			`fs-lint`
125	131	jt_eaton
126	135	jt_eaton
127			`dest_dir`
128			`../views/syn/`
129			`verilogSource`
130			`libraryDir`
131
132	131	jt_eaton
133	135	jt_eaton
134	131	jt_eaton
135
136
137
138
139
140	135	jt_eaton
141	131	jt_eaton
142
143
144
145
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151
152	135	jt_eaton
153	131	jt_eaton
154
155
156
157	135	jt_eaton
158			`sim`
159			`:Simulation:`
160			`Verilog`
161
162			`fs-sim`
163
164	131	jt_eaton
165
166	135	jt_eaton
167			`syn`
168			`:Synthesis:`
169			`Verilog`
170
171			`fs-syn`
172
173	131	jt_eaton
174
175
176	135	jt_eaton
177			`lint`
178			`:Lint:`
179			`Verilog`
180
181			`fs-lint`
182
183	131	jt_eaton
184
185
186
187
188
189
190
191	135	jt_eaton
192	131	jt_eaton
193
194
195	135	jt_eaton
196	131	jt_eaton
197	135	jt_eaton
198	131	jt_eaton
199
200
201
202
203

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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [toolflows/] [toolflow/] [xml/] [verilog.xml] - Blame information for rev 135