Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

cde

clock

dll

 ref_clk

             clk

             ref_clk

 dll_clk_out

             clk

             dll_clk_out

 reset

            reset

            reset

  gen_verilog_sim

  104.0

  none

  :*Simulation:*

  tools/verilog/gen_verilog

      destination

      clock_dll

  gen_verilog_syn

  104.0

  none

  :*Synthesis:*

  tools/verilog/gen_verilog

      destination

      clock_dll

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

DIV4

MULT2

SIZE4

ref_clk

wire

in

reset

wire

in

dll_clk_out

reg

out

div_clk_out

reg

out

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/timescale

        verilogSourceinclude

        ../verilog/sim/dll

        verilogSourcefragment

        ../verilog/sim/clock_dll

        verilogSourcemodule

        dest_dir

        ../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/syn/dll

        verilogSourcefragment

        ../verilog/syn/clock_dll

        verilogSourcemodule

        dest_dir

        ../views/syn/

        verilogSourcelibraryDir

      fs-lint

        dest_dir../views/syn/

        verilogSourcelibraryDir