Subversion Repositories socgen

xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014

http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">

opencores.org

cde

divider

def

 slave_clk

        clk

        clk

  slave_reset

        reset

        reset

  slave_enable

        enable

        enable

  divider_in

        adhoc

        divider_in

  divider_out

        adhoc

        divider_out

  gen_verilog

  104.0

  none

  :*common:*

  tools/verilog/gen_verilog

      destination

      divider_def

        verilog

        verilog

        cde_divider_def

                                SIZE

                                4

                        fs-sim

        rtl

        verilog:Kactus2:

        verilog

              verilog

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="verilog"/>

              common:*common:*

              Verilog

                            fs-common

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   ipxact:library="Testbench"

                                   ipxact:name="toolflow"

                                   ipxact:version="documentation"/>

              :*Documentation:*

              Verilog

SIZE4

SAMPLE0

RESET1

clk

wire

in

reset

wire

in

enable

wire

in

divider_in

wire

in

SIZE-10

divider_out

reg

out

      fs-common

        ../verilog/divider_def

        verilogSourcefragment

      fs-sim

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/common/divider_def

        verilogSourcemodule

        dest_dir

        ../views/sim/

        verilogSourcelibraryDir

      fs-syn

        ../verilog/copyright

        verilogSourceinclude

        ../verilog/common/divider_def

        verilogSourcemodule

        dest_dir

        ../views/syn/

        verilogSourcelibraryDir

      fs-lint

        dest_dir

        ../views/syn/

        verilogSourcelibraryDir