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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [fifo/] [sim/] [testbenches/] [xml/] [cde_fifo_def_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
fifo
def_tb
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      fifo_def_tb
    
  

 
 
 

 
 
 
 
 
 
 



 
       
 
              
              Params
              
              
                                   ipxact:library="cde"
                                   ipxact:name="fifo"
                                   ipxact:version="def_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   ipxact:library="cde"
                                   ipxact:name="fifo"
                                   ipxact:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 

 
 
 
 
 

 
 
   
      fs-common
 
      
        
        ../verilog/tb
        verilogSourcefragment
      
 
 
 
   
 
 
   
      fs-sim
 
 
 
      
        
        ../verilog/common/fifo_def_tb
        verilogSourcemodule
      
 
 
   
 
 
   
      fs-lint
      
        
        ../verilog/common/fifo_def_tb
        verilogSourcemodule
      
 
 
   
 
 
 
 
 

 
 
 
 
 


Line No.	Rev	Author	Line
1	134	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	134	jt_eaton	`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	134	jt_eaton
12	135	jt_eaton	`opencores.org`
13			`cde`
14			`fifo`
15			`def_tb`
16	134	jt_eaton
17
18
19	135	jt_eaton
20	134	jt_eaton
21
22
23
24	135	jt_eaton
25			`gen_verilog`
26			`104.0`
27			`none`
28			`:common:`
29			`tools/verilog/gen_verilog`
30
31
32			`destination`
33			`fifo_def_tb`
34
35
36
37	134	jt_eaton
38
39
40	135	jt_eaton
41	134	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49
50
51	134	jt_eaton
52	135	jt_eaton
53	134	jt_eaton
54	135	jt_eaton
55			`Params`
56
57
58			`ipxact:library="cde"`
59			`ipxact:name="fifo"`
60			`ipxact:version="def_dut.params"/>`
61
62
63	134	jt_eaton
64
65	135	jt_eaton
66			`Bfm`
67
68			`ipxact:library="cde"`
69			`ipxact:name="fifo"`
70			`ipxact:version="bfm.design"/>`
71
72	134	jt_eaton
73
74	135	jt_eaton
75			`icarus`
76
77
78			`ipxact:library="Testbench"`
79			`ipxact:name="toolflow"`
80			`ipxact:version="icarus"/>`
81
82
83	134	jt_eaton
84
85
86
87	135	jt_eaton
88			`common:common:`
89			`Verilog`
90
91
92			`fs-common`
93
94
95	134	jt_eaton
96
97	135	jt_eaton
98			`sim:Simulation:`
99			`Verilog`
100
101
102			`fs-sim`
103
104
105	134	jt_eaton
106	135	jt_eaton
107			`lint:Lint:`
108			`Verilog`
109
110
111			`fs-lint`
112
113
114	134	jt_eaton
115	135	jt_eaton
116	134	jt_eaton
117
118
119
120	135	jt_eaton
121	134	jt_eaton
122
123
124
125
126	135	jt_eaton
127	134	jt_eaton
128
129	135	jt_eaton
130			`fs-common`
131	134	jt_eaton
132	135	jt_eaton
133
134			`../verilog/tb`
135			`verilogSourcefragment`
136
137	134	jt_eaton
138
139
140	135	jt_eaton
141	134	jt_eaton
142
143	135	jt_eaton
144			`fs-sim`
145	134	jt_eaton
146
147
148	135	jt_eaton
149
150			`../verilog/common/fifo_def_tb`
151			`verilogSourcemodule`
152
153	134	jt_eaton
154
155	135	jt_eaton
156	134	jt_eaton
157
158	135	jt_eaton
159			`fs-lint`
160
161
162			`../verilog/common/fifo_def_tb`
163			`verilogSourcemodule`
164
165	134	jt_eaton
166
167	135	jt_eaton
168	134	jt_eaton
169
170
171
172
173	135	jt_eaton
174	134	jt_eaton
175
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177	135	jt_eaton
178
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [fifo/] [sim/] [testbenches/] [xml/] [cde_fifo_def_tb.xml] - Blame information for rev 135