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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_and.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
gates
and
 
 

 
 

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      fs-sim
 
       
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        verilogSourceinclude
      
 
 
      
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        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
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      fs-syn
 
 
       
        ../verilog/and
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        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_and
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
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                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
IN0
wire
in

 
IN1
wire
in

 
 
 
OUT
wire
out

 
 
 
 
 

 

 
 
 
 
 
 

 
 

 
 
 
 

refdes
U?
300
900
5
10
1
1
2

 

module_name
cde_gates_and
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
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0

 

library
cde
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component
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version
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cde_gates_and
 
 

 geda-project.org
 symbols
 gates
 def
 and
 0
 100

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 200
 IN1
0

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 600
 IN0
0

 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1000
 400
 OUT
0

 
 

 
 
 
 
 

 
demorgan
 

 geda-project.org
 symbols
 gates
 def
 or
 0
 100

 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire_n
 0
 200
 IN1
 0

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire_n
 0
 600
 IN0
0

 
 
 

 
 geda-project.org
 symbols
 pins
 def
 out_wire_n
 1000
 400
 OUT
 0

 

 
 
 
 

 
 


 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_and.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`gates`
15			`and`
16
17
18
19
20
21
22			`gen_verilog_sim`
23			`104.0`
24			`none`
25			`:Simulation:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`gates_and`
31
32
33
34
35
36
37			`gen_verilog_syn`
38			`104.0`
39			`none`
40			`:Synthesis:`
41			`tools/verilog/gen_verilog`
42
43
44			`destination`
45			`gates_and`
46
47
48
49
50
51
52
53
54			`gen_verilogLib_sim`
55			`105.0`
56			`none`
57			`:Simulation:`
58			`tools/verilog/gen_verilogLib`
59
60
61			`dest_dir`
62			`../views`
63
64
65			`view`
66			`sim`
67
68
69
70
71
72
73
74			`gen_verilogLib_syn`
75			`105.0`
76			`none`
77			`:Synthesis:`
78			`tools/verilog/gen_verilogLib`
79
80
81			`dest_dir`
82			`../views`
83
84
85			`view`
86			`syn`
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107			`fs-sim`
108
109
110			`../verilog/and`
111			`verilogSourcefragment`
112
113
114
115
116			`../verilog/copyright`
117			`verilogSourceinclude`
118
119
120
121
122			`../verilog/sim/gates_and`
123			`verilogSourcemodule`
124
125
126
127
128
129			`dest_dir`
130			`../views/sim/`
131			`verilogSourcelibraryDir`
132
133
134
135
136
137
138			`fs-syn`
139
140
141
142			`../verilog/and`
143			`verilogSourcefragment`
144
145
146
147
148			`../verilog/copyright`
149			`verilogSourceinclude`
150
151
152
153
154			`../verilog/sim/gates_and`
155			`verilogSourcemodule`
156
157
158
159
160
161
162			`dest_dir`
163			`../views/syn/`
164			`verilogSourcelibraryDir`
165
166
167
168
169
170
171
172
173
174			`fs-lint`
175
176			`dest_dir`
177			`../views/syn/`
178			`verilogSourcelibraryDir`
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200			`sim:Simulation:`
201			`Verilog`
202
203
204			`fs-sim`
205
206
207
208
209			`syn:Synthesis:`
210			`Verilog`
211
212
213			`fs-syn`
214
215
216
217
218
219			`doc`
220
221
222			`ipxact:library="Testbench"`
223			`ipxact:name="toolflow"`
224			`ipxact:version="documentation"/>`
225
226			`:Documentation:`
227			`Verilog`
228
229
230
231
232
233
234
235
236
237
238
239
240			`IN0`
241			`wire`
242			`in`
243
244
245			`IN1`
246			`wire`
247			`in`
248
249
250
251
252			`OUT`
253			`wire`
254			`out`
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279			`refdes`
280			`U?`
281			`300`
282			`900`
283			`5`
284			`10`
285			`1`
286			`1`
287			`2`
288
289
290
291			`module_name`
292			`cde_gates_and`
293			`400`
294			`0`
295			`5`
296			`10`
297			`0`
298			`1`
299			`2`
300
301
302
303			`vendor`
304			`opencores.org`
305			`0`
306			`-200`
307			`0`
308			`10`
309			`0`
310			`0`
311			`0`
312
313
314
315			`library`
316			`cde`
317			`0`
318			`-300`
319			`0`
320			`10`
321			`0`
322			`0`
323			`0`
324
325
326
327
328			`component`
329			`gates`
330			`0`
331			`-400`
332			`0`
333			`10`
334			`0`
335			`0`
336			`0`
337
338
339
340
341
342			`version`
343			`and`
344			`0`
345			`-500`
346			`0`
347			`10`
348			`0`
349			`0`
350			`0`
351
352
353
354
355
356
357
358
359
360
361
362
363			`cde_gates_and`
364
365
366
367			`geda-project.org`
368			`symbols`
369			`gates`
370			`def`
371			`and`
372			`0`
373			`100`
374
375
376
377
378
379
380			`geda-project.org`
381			`symbols`
382			`pins`
383			`def`
384			`in_wire`
385			`0`
386			`200`
387			`IN1`
388			`0`
389
390
391
392
393			`geda-project.org`
394			`symbols`
395			`pins`
396			`def`
397			`in_wire`
398			`0`
399			`600`
400			`IN0`
401			`0`
402
403
404
405
406
407			`geda-project.org`
408			`symbols`
409			`pins`
410			`def`
411			`out_wire`
412			`1000`
413			`400`
414			`OUT`
415			`0`
416
417
418
419
420
421
422
423
424
425
426
427			`demorgan`
428
429
430			`geda-project.org`
431			`symbols`
432			`gates`
433			`def`
434			`or`
435			`0`
436			`100`
437
438
439
440
441
442			`geda-project.org`
443			`symbols`
444			`pins`
445			`def`
446			`in_wire_n`
447			`0`
448			`200`
449			`IN1`
450			`0`
451
452
453
454
455			`geda-project.org`
456			`symbols`
457			`pins`
458			`def`
459			`in_wire_n`
460			`0`
461			`600`
462			`IN0`
463			`0`
464
465
466
467
468
469
470			`geda-project.org`
471			`symbols`
472			`pins`
473			`def`
474			`out_wire_n`
475			`1000`
476			`400`
477			`OUT`
478			`0`
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498