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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_inv.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
gates
inv
 
 

 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      gates_inv
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      gates_inv
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 

 
 

 
 
 
 
 
 
 
 

refdes
U?
600
700
5
10
1
1
2

 

module_name
cde_gates_inv
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
gates
0
-400
0
10
0
0
0

 
 
 

version
inv
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_gates_inv
 
 

 geda-project.org
 symbols
 gates
 def
 buf
 0
 0

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 400
 IN
0

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire_n
 800
 400
 OUT
0

 
 

 
 
 
 
 

 
vector
 
 
 
 

 geda-project.org
 symbols
 gates
 def
 buf
 0
 0

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 400
 IN
 0

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus_n
 800
 400
 OUT
 0

 
 

 
 
 
 
 
 
 
 
 

 
 


 
 
 
 
 
 

 
   
      fs-sim
 
       
        ../verilog/inv
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_inv
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
       
        ../verilog/inv
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_inv
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
            
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
IN
wire
in

 
 
 
OUT
wire
out

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_inv.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`gates`
15			`inv`
16
17
18
19
20
21
22			`gen_verilog_sim`
23			`104.0`
24			`none`
25			`:Simulation:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`gates_inv`
31
32
33
34
35
36
37			`gen_verilog_syn`
38			`104.0`
39			`none`
40			`:Synthesis:`
41			`tools/verilog/gen_verilog`
42
43
44			`destination`
45			`gates_inv`
46
47
48
49
50
51
52
53
54			`gen_verilogLib_sim`
55			`105.0`
56			`none`
57			`:Simulation:`
58			`tools/verilog/gen_verilogLib`
59
60
61			`dest_dir`
62			`../views`
63
64
65			`view`
66			`sim`
67
68
69
70
71
72
73
74			`gen_verilogLib_syn`
75			`105.0`
76			`none`
77			`:Synthesis:`
78			`tools/verilog/gen_verilogLib`
79
80
81			`dest_dir`
82			`../views`
83
84
85			`view`
86			`syn`
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108			`refdes`
109			`U?`
110			`600`
111			`700`
112			`5`
113			`10`
114			`1`
115			`1`
116			`2`
117
118
119
120			`module_name`
121			`cde_gates_inv`
122			`400`
123			`0`
124			`5`
125			`10`
126			`0`
127			`1`
128			`2`
129
130
131
132			`vendor`
133			`opencores.org`
134			`0`
135			`-200`
136			`0`
137			`10`
138			`0`
139			`0`
140			`0`
141
142
143
144			`library`
145			`cde`
146			`0`
147			`-300`
148			`0`
149			`10`
150			`0`
151			`0`
152			`0`
153
154
155
156
157			`component`
158			`gates`
159			`0`
160			`-400`
161			`0`
162			`10`
163			`0`
164			`0`
165			`0`
166
167
168
169
170
171			`version`
172			`inv`
173			`0`
174			`-500`
175			`0`
176			`10`
177			`0`
178			`0`
179			`0`
180
181
182
183
184
185
186
187
188
189
190
191
192			`cde_gates_inv`
193
194
195
196			`geda-project.org`
197			`symbols`
198			`gates`
199			`def`
200			`buf`
201			`0`
202			`0`
203
204
205
206
207
208
209			`geda-project.org`
210			`symbols`
211			`pins`
212			`def`
213			`in_wire`
214			`0`
215			`400`
216			`IN`
217			`0`
218
219
220
221
222
223
224			`geda-project.org`
225			`symbols`
226			`pins`
227			`def`
228			`out_wire_n`
229			`800`
230			`400`
231			`OUT`
232			`0`
233
234
235
236
237
238
239
240
241
242
243
244			`vector`
245
246
247
248
249
250			`geda-project.org`
251			`symbols`
252			`gates`
253			`def`
254			`buf`
255			`0`
256			`0`
257
258
259
260
261
262
263			`geda-project.org`
264			`symbols`
265			`pins`
266			`def`
267			`in_bus`
268			`0`
269			`400`
270			`IN`
271			`0`
272
273
274
275
276
277
278			`geda-project.org`
279			`symbols`
280			`pins`
281			`def`
282			`out_bus_n`
283			`800`
284			`400`
285			`OUT`
286			`0`
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314			`fs-sim`
315
316
317			`../verilog/inv`
318			`verilogSourcefragment`
319
320
321
322
323			`../verilog/copyright`
324			`verilogSourceinclude`
325
326
327
328
329			`../verilog/sim/gates_inv`
330			`verilogSourcemodule`
331
332
333
334
335
336			`dest_dir`
337			`../views/sim/`
338			`verilogSourcelibraryDir`
339
340
341
342
343
344
345			`fs-syn`
346
347
348
349			`../verilog/inv`
350			`verilogSourcefragment`
351
352
353
354
355			`../verilog/copyright`
356			`verilogSourceinclude`
357
358
359
360
361			`../verilog/sim/gates_inv`
362			`verilogSourcemodule`
363
364
365
366
367
368
369			`dest_dir`
370			`../views/syn/`
371			`verilogSourcelibraryDir`
372
373
374
375
376
377
378
379
380
381			`fs-lint`
382
383			`dest_dir`
384			`../views/syn/`
385			`verilogSourcelibraryDir`
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407			`sim:Simulation:`
408			`Verilog`
409
410
411			`fs-sim`
412
413
414
415
416			`syn:Synthesis:`
417			`Verilog`
418
419
420			`fs-syn`
421
422
423
424
425
426			`doc`
427
428
429			`ipxact:library="Testbench"`
430			`ipxact:name="toolflow"`
431			`ipxact:version="documentation"/>`
432
433			`:Documentation:`
434			`Verilog`
435
436
437
438
439
440
441
442
443
444
445
446
447			`IN`
448			`wire`
449			`in`
450
451
452
453
454			`OUT`
455			`wire`
456			`out`
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479