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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_mux.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
gates
mux
 
 

 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      gates_mux
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      gates_mux
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 

 
 

 

 geda-project.org
 symbols
 gates
 mux
 mux
 0
 0

 
 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 800
 SEL
1

 
 
 
 
 

refdes
U?
700
 200
5
10
1
1
2

 

module_name
cde_gates_mux
400
0
5
10
1
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
gates
0
-400
0
10
0
0
0

 
 
 

version
mux
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_gates_mux
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 300
 IN1
 1

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 500
 IN0
 1

 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire
 1000
 600
 OUT
 1

 
 

 
 
 
 

 
vector
 

WIDTH
1
0
-600
0
0
0
0
0

 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 300
 IN1
 1

 
 

 geda-project.org
 symbols
 pins
 def
 in_bus
 0
 500
 IN0
 1

 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus
 1000
 600
 OUT
 1

 

 
 
 
 
 
 
 
 

 
demorgan
 

 geda-project.org
 symbols
 pins
 def
 in_wire_n
 0
 300
 IN1
 1

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire_n
 0
 500
 IN0
 1

 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire_n
 1000
 600
 OUT
 1

 

 
 
 

 
demorgan_bus
 

 geda-project.org
 symbols
 pins
 def
 in_bus_n
 0
 300
 IN1
 1

 
 

 geda-project.org
 symbols
 pins
 def
 in_bus_n
 0
 500
 IN0
 1

 
 
 

 geda-project.org
 symbols
 pins
 def
 out_bus_n
 1000
 600
 OUT
 1

 

 
 
 
 
 

 
 


 
 
 
 
 
 

 
   
      fs-sim
 
       
        ../verilog/mux
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_mux
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
       
        ../verilog/mux
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_mux
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
            
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
sel
wire
in

 
IN0
wire
in

 
IN1
wire
in

 
 
 
OUT
wire
out

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_mux.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`gates`
15			`mux`
16
17
18
19
20
21
22			`gen_verilog_sim`
23			`104.0`
24			`none`
25			`:Simulation:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`gates_mux`
31
32
33
34
35
36
37			`gen_verilog_syn`
38			`104.0`
39			`none`
40			`:Synthesis:`
41			`tools/verilog/gen_verilog`
42
43
44			`destination`
45			`gates_mux`
46
47
48
49
50
51
52
53
54			`gen_verilogLib_sim`
55			`105.0`
56			`none`
57			`:Simulation:`
58			`tools/verilog/gen_verilogLib`
59
60
61			`dest_dir`
62			`../views`
63
64
65			`view`
66			`sim`
67
68
69
70
71
72
73
74			`gen_verilogLib_syn`
75			`105.0`
76			`none`
77			`:Synthesis:`
78			`tools/verilog/gen_verilogLib`
79
80
81			`dest_dir`
82			`../views`
83
84
85			`view`
86			`syn`
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101			`geda-project.org`
102			`symbols`
103			`gates`
104			`mux`
105			`mux`
106			`0`
107			`0`
108
109
110
111
112
113
114
115			`geda-project.org`
116			`symbols`
117			`pins`
118			`def`
119			`in_wire`
120			`0`
121			`800`
122			`SEL`
123			`1`
124
125
126
127
128
129
130
131			`refdes`
132			`U?`
133			`700`
134			`200`
135			`5`
136			`10`
137			`1`
138			`1`
139			`2`
140
141
142
143			`module_name`
144			`cde_gates_mux`
145			`400`
146			`0`
147			`5`
148			`10`
149			`1`
150			`1`
151			`2`
152
153
154
155			`vendor`
156			`opencores.org`
157			`0`
158			`-200`
159			`0`
160			`10`
161			`0`
162			`0`
163			`0`
164
165
166
167			`library`
168			`cde`
169			`0`
170			`-300`
171			`0`
172			`10`
173			`0`
174			`0`
175			`0`
176
177
178
179
180			`component`
181			`gates`
182			`0`
183			`-400`
184			`0`
185			`10`
186			`0`
187			`0`
188			`0`
189
190
191
192
193
194			`version`
195			`mux`
196			`0`
197			`-500`
198			`0`
199			`10`
200			`0`
201			`0`
202			`0`
203
204
205
206
207
208
209
210
211
212
213
214
215			`cde_gates_mux`
216
217
218
219
220			`geda-project.org`
221			`symbols`
222			`pins`
223			`def`
224			`in_wire`
225			`0`
226			`300`
227			`IN1`
228			`1`
229
230
231
232
233			`geda-project.org`
234			`symbols`
235			`pins`
236			`def`
237			`in_wire`
238			`0`
239			`500`
240			`IN0`
241			`1`
242
243
244
245
246
247			`geda-project.org`
248			`symbols`
249			`pins`
250			`def`
251			`out_wire`
252			`1000`
253			`600`
254			`OUT`
255			`1`
256
257
258
259
260
261
262
263
264
265
266			`vector`
267
268
269			`WIDTH`
270			`1`
271			`0`
272			`-600`
273			`0`
274			`0`
275			`0`
276			`0`
277			`0`
278
279
280
281
282			`geda-project.org`
283			`symbols`
284			`pins`
285			`def`
286			`in_bus`
287			`0`
288			`300`
289			`IN1`
290			`1`
291
292
293
294
295			`geda-project.org`
296			`symbols`
297			`pins`
298			`def`
299			`in_bus`
300			`0`
301			`500`
302			`IN0`
303			`1`
304
305
306
307
308
309			`geda-project.org`
310			`symbols`
311			`pins`
312			`def`
313			`out_bus`
314			`1000`
315			`600`
316			`OUT`
317			`1`
318
319
320
321
322
323
324
325
326
327
328
329
330
331			`demorgan`
332
333
334			`geda-project.org`
335			`symbols`
336			`pins`
337			`def`
338			`in_wire_n`
339			`0`
340			`300`
341			`IN1`
342			`1`
343
344
345
346
347			`geda-project.org`
348			`symbols`
349			`pins`
350			`def`
351			`in_wire_n`
352			`0`
353			`500`
354			`IN0`
355			`1`
356
357
358
359
360
361			`geda-project.org`
362			`symbols`
363			`pins`
364			`def`
365			`out_wire_n`
366			`1000`
367			`600`
368			`OUT`
369			`1`
370
371
372
373
374
375
376
377
378			`demorgan_bus`
379
380
381			`geda-project.org`
382			`symbols`
383			`pins`
384			`def`
385			`in_bus_n`
386			`0`
387			`300`
388			`IN1`
389			`1`
390
391
392
393
394			`geda-project.org`
395			`symbols`
396			`pins`
397			`def`
398			`in_bus_n`
399			`0`
400			`500`
401			`IN0`
402			`1`
403
404
405
406
407
408			`geda-project.org`
409			`symbols`
410			`pins`
411			`def`
412			`out_bus_n`
413			`1000`
414			`600`
415			`OUT`
416			`1`
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439			`fs-sim`
440
441
442			`../verilog/mux`
443			`verilogSourcefragment`
444
445
446
447
448			`../verilog/copyright`
449			`verilogSourceinclude`
450
451
452
453
454			`../verilog/sim/gates_mux`
455			`verilogSourcemodule`
456
457
458
459
460
461			`dest_dir`
462			`../views/sim/`
463			`verilogSourcelibraryDir`
464
465
466
467
468
469
470			`fs-syn`
471
472
473
474			`../verilog/mux`
475			`verilogSourcefragment`
476
477
478
479
480			`../verilog/copyright`
481			`verilogSourceinclude`
482
483
484
485
486			`../verilog/sim/gates_mux`
487			`verilogSourcemodule`
488
489
490
491
492
493
494			`dest_dir`
495			`../views/syn/`
496			`verilogSourcelibraryDir`
497
498
499
500
501
502
503
504
505
506			`fs-lint`
507
508			`dest_dir`
509			`../views/syn/`
510			`verilogSourcelibraryDir`
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532			`sim:Simulation:`
533			`Verilog`
534
535
536			`fs-sim`
537
538
539
540
541			`syn:Synthesis:`
542			`Verilog`
543
544
545			`fs-syn`
546
547
548
549
550
551			`doc`
552
553
554			`ipxact:library="Testbench"`
555			`ipxact:name="toolflow"`
556			`ipxact:version="documentation"/>`
557
558			`:Documentation:`
559			`Verilog`
560
561
562
563
564
565
566
567
568
569
570
571
572			`sel`
573			`wire`
574			`in`
575
576
577			`IN0`
578			`wire`
579			`in`
580
581
582			`IN1`
583			`wire`
584			`in`
585
586
587
588
589			`OUT`
590			`wire`
591			`out`
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614