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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_nor.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
cde
gates
nor
 
 

 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  tools/verilog/gen_verilog
    
    
      destination
      gates_nor
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilog
    
    
      destination
      gates_nor
    
  

 
 
 
 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      sim
    
  

 
 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
    
      view
      syn
    
  

 
 
 

 

 
 

 
 
 
 

refdes
U?
300
900
5
10
1
1
2

 

module_name
cde_gates_nor
400
0
5
10
0
1
2

 

vendor
opencores.org
0
-200
0
10
0
0
0

 

library
cde
0
-300
0
10
0
0
0

 
 

component
gates
0
-400
0
10
0
0
0

 
 
 

version
nor
0
-500
0
10
0
0
0

 
 
 
 
 
 
 
 

 

cde_gates_nor
 
 

 geda-project.org
 symbols
 gates
 def
 or
 0
 100

 
 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 200
 IN1
0

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire
 0
 600
 IN0
0

 
 
 

 geda-project.org
 symbols
 pins
 def
 out_wire_n
 1000
 400
 OUT
0

 
 

 
 
 
 
 

 
demorgan
 

 geda-project.org
 symbols
 gates
 def
 and
 0
 100

 
 
 

 geda-project.org
 symbols
 pins
 def
 in_wire_n
 0
 200
 IN1
0

 
 

 geda-project.org
 symbols
 pins
 def
 in_wire_n
 0
 600
 IN0
0

 
 
 

 
 geda-project.org
 symbols
 pins
 def
 out_wire
 1000
 400
 OUT
0

 

 
 
 
 

 
 


 
 
 
 
 
 

 
   
      fs-sim
 
       
        ../verilog/nor
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_nor
        verilogSourcemodule
      
 
 
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
 
       
        ../verilog/nor
        verilogSourcefragment
      
 
 
      
        ../verilog/copyright
        verilogSourceinclude
      
 
 
      
        ../verilog/sim/gates_nor
        verilogSourcemodule
      
 
 
 
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
    
 
      fs-lint
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 

 
 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
            
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
      
 
 
 
 

 
IN0
wire
in

 
IN1
wire
in

 
 
 
OUT
wire
out

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [rtl/] [xml/] [cde_gates_nor.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11
12			`opencores.org`
13			`cde`
14			`gates`
15			`nor`
16
17
18
19
20
21
22			`gen_verilog_sim`
23			`104.0`
24			`none`
25			`:Simulation:`
26			`tools/verilog/gen_verilog`
27
28
29			`destination`
30			`gates_nor`
31
32
33
34
35
36
37			`gen_verilog_syn`
38			`104.0`
39			`none`
40			`:Synthesis:`
41			`tools/verilog/gen_verilog`
42
43
44			`destination`
45			`gates_nor`
46
47
48
49
50
51
52
53
54			`gen_verilogLib_sim`
55			`105.0`
56			`none`
57			`:Simulation:`
58			`tools/verilog/gen_verilogLib`
59
60
61			`dest_dir`
62			`../views`
63
64
65			`view`
66			`sim`
67
68
69
70
71
72
73
74			`gen_verilogLib_syn`
75			`105.0`
76			`none`
77			`:Synthesis:`
78			`tools/verilog/gen_verilogLib`
79
80
81			`dest_dir`
82			`../views`
83
84
85			`view`
86			`syn`
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104			`refdes`
105			`U?`
106			`300`
107			`900`
108			`5`
109			`10`
110			`1`
111			`1`
112			`2`
113
114
115
116			`module_name`
117			`cde_gates_nor`
118			`400`
119			`0`
120			`5`
121			`10`
122			`0`
123			`1`
124			`2`
125
126
127
128			`vendor`
129			`opencores.org`
130			`0`
131			`-200`
132			`0`
133			`10`
134			`0`
135			`0`
136			`0`
137
138
139
140			`library`
141			`cde`
142			`0`
143			`-300`
144			`0`
145			`10`
146			`0`
147			`0`
148			`0`
149
150
151
152
153			`component`
154			`gates`
155			`0`
156			`-400`
157			`0`
158			`10`
159			`0`
160			`0`
161			`0`
162
163
164
165
166
167			`version`
168			`nor`
169			`0`
170			`-500`
171			`0`
172			`10`
173			`0`
174			`0`
175			`0`
176
177
178
179
180
181
182
183
184
185
186
187
188			`cde_gates_nor`
189
190
191
192			`geda-project.org`
193			`symbols`
194			`gates`
195			`def`
196			`or`
197			`0`
198			`100`
199
200
201
202
203
204
205			`geda-project.org`
206			`symbols`
207			`pins`
208			`def`
209			`in_wire`
210			`0`
211			`200`
212			`IN1`
213			`0`
214
215
216
217
218			`geda-project.org`
219			`symbols`
220			`pins`
221			`def`
222			`in_wire`
223			`0`
224			`600`
225			`IN0`
226			`0`
227
228
229
230
231
232			`geda-project.org`
233			`symbols`
234			`pins`
235			`def`
236			`out_wire_n`
237			`1000`
238			`400`
239			`OUT`
240			`0`
241
242
243
244
245
246
247
248
249
250
251
252			`demorgan`
253
254
255			`geda-project.org`
256			`symbols`
257			`gates`
258			`def`
259			`and`
260			`0`
261			`100`
262
263
264
265
266
267			`geda-project.org`
268			`symbols`
269			`pins`
270			`def`
271			`in_wire_n`
272			`0`
273			`200`
274			`IN1`
275			`0`
276
277
278
279
280			`geda-project.org`
281			`symbols`
282			`pins`
283			`def`
284			`in_wire_n`
285			`0`
286			`600`
287			`IN0`
288			`0`
289
290
291
292
293
294
295			`geda-project.org`
296			`symbols`
297			`pins`
298			`def`
299			`out_wire`
300			`1000`
301			`400`
302			`OUT`
303			`0`
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325			`fs-sim`
326
327
328			`../verilog/nor`
329			`verilogSourcefragment`
330
331
332
333
334			`../verilog/copyright`
335			`verilogSourceinclude`
336
337
338
339
340			`../verilog/sim/gates_nor`
341			`verilogSourcemodule`
342
343
344
345
346
347			`dest_dir`
348			`../views/sim/`
349			`verilogSourcelibraryDir`
350
351
352
353
354
355
356			`fs-syn`
357
358
359
360			`../verilog/nor`
361			`verilogSourcefragment`
362
363
364
365
366			`../verilog/copyright`
367			`verilogSourceinclude`
368
369
370
371
372			`../verilog/sim/gates_nor`
373			`verilogSourcemodule`
374
375
376
377
378
379
380			`dest_dir`
381			`../views/syn/`
382			`verilogSourcelibraryDir`
383
384
385
386
387
388
389
390
391
392			`fs-lint`
393
394			`dest_dir`
395			`../views/syn/`
396			`verilogSourcelibraryDir`
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418			`sim:Simulation:`
419			`Verilog`
420
421
422			`fs-sim`
423
424
425
426
427			`syn:Synthesis:`
428			`Verilog`
429
430
431			`fs-syn`
432
433
434
435
436
437			`doc`
438
439
440			`ipxact:library="Testbench"`
441			`ipxact:name="toolflow"`
442			`ipxact:version="documentation"/>`
443
444			`:Documentation:`
445			`Verilog`
446
447
448
449
450
451
452
453
454
455
456
457
458			`IN0`
459			`wire`
460			`in`
461
462
463			`IN1`
464			`wire`
465			`in`
466
467
468
469
470			`OUT`
471			`wire`
472			`out`
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
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