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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [gates/] [sim/] [testbenches/] [xml/] [cde_gates_sys_lint.xml] - Blame information for rev 135

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1 135 jt_eaton
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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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cde
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gates
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sys_lint
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                Bfm
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              Bfm
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              Bfm
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              lint
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              :*Lint:*
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              Verilog
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              fs-lint
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              rtl_check
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                                   ipxact:library="Testbench"
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                                   ipxact:name="toolflow"
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                                   ipxact:version="rtl_check"/>
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      fs-lint
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        ../verilog/lint/gates_sys_lint
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        verilogSource
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        module
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