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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [doc/] [sch/] [cde_jtag_tap.sch] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
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C 1500 300 1 0 0 in_port.sym
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{
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T 1500 300 5 10 1 1 0 6 1 1
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refdes=trst_n_pad_in
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}
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C 1500 700 1 0 0 in_port.sym
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{
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T 1500 700 5 10 1 1 0 6 1 1
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refdes=tms_pad_in
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}
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C 1500 1100 1 0 0 in_port.sym
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{
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T 1500 1100 5 10 1 1 0 6 1 1
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refdes=tdo_i
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}
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C 1500 1500 1 0 0 in_port.sym
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{
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T 1500 1500 5 10 1 1 0 6 1 1
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refdes=tdi_pad_in
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}
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C 1500 1900 1 0 0 in_port.sym
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{
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T 1500 1900 5 10 1 1 0 6 1 1
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refdes=tclk_pad_in
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}
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C 1500 2300 1 0 0 in_port.sym
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{
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T 1500 2300 5 10 1 1 0 6 1 1
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refdes=bsr_tdo_i
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}
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C 1500 2700 1 0 0 in_port.sym
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{
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T 1500 2700 5 10 1 1 0 6 1 1
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refdes=aux_tdo_i
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}
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C 5300 300  1 0 0 out_port.sym
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{
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T 6300 300 5  10 1 1 0 0 1 1
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refdes=update_dr_o
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}
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C 5300 700  1 0 0 out_port.sym
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{
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T 6300 700 5  10 1 1 0 0 1 1
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refdes=update_dr_clk_o
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}
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C 5300 1100  1 0 0 out_port.sym
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{
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T 6300 1100 5  10 1 1 0 0 1 1
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refdes=test_logic_reset_o
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}
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C 5300 1500  1 0 0 out_port.sym
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{
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T 6300 1500 5  10 1 1 0 0 1 1
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refdes=tdo_pad_out
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}
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C 5300 1900  1 0 0 out_port.sym
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{
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T 6300 1900 5  10 1 1 0 0 1 1
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refdes=tdo_pad_oe
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}
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C 5300 2300  1 0 0 out_port.sym
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{
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T 6300 2300 5  10 1 1 0 0 1 1
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refdes=tdi_o
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}
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C 5300 2700  1 0 0 out_port.sym
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{
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T 6300 2700 5  10 1 1 0 0 1 1
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refdes=tap_highz_mode
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}
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C 5300 3100  1 0 0 out_port.sym
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{
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T 6300 3100 5  10 1 1 0 0 1 1
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refdes=shiftcapture_dr_clk_o
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}
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C 5300 3500  1 0 0 out_port.sym
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{
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T 6300 3500 5  10 1 1 0 0 1 1
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refdes=shift_dr_o
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}
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C 5300 3900  1 0 0 out_port.sym
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{
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T 6300 3900 5  10 1 1 0 0 1 1
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refdes=select_o
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}
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C 5300 4300  1 0 0 out_port.sym
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{
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T 6300 4300 5  10 1 1 0 0 1 1
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refdes=jtag_clk
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}
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C 5300 4700  1 0 0 out_port.sym
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{
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T 6300 4700 5  10 1 1 0 0 1 1
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refdes=capture_dr_o
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}
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C 5300 5100  1 0 0 out_port.sym
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{
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T 6300 5100 5  10 1 1 0 0 1 1
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refdes=bsr_select_o
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}
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C 5300 5500  1 0 0 out_port.sym
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{
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T 6300 5500 5  10 1 1 0 0 1 1
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refdes=bsr_output_mode
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}
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C 5300 5900  1 0 0 out_port.sym
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{
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T 6300 5900 5  10 1 1 0 0 1 1
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refdes=aux_update_dr_clk_o
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}
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C 5300 6300  1 0 0 out_port.sym
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{
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T 6300 6300 5  10 1 1 0 0 1 1
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refdes=aux_test_logic_reset_o
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}
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C 5300 6700  1 0 0 out_port.sym
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{
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T 6300 6700 5  10 1 1 0 0 1 1
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refdes=aux_tdi_o
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}
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C 5300 7100  1 0 0 out_port.sym
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{
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T 6300 7100 5  10 1 1 0 0 1 1
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refdes=aux_shiftcapture_dr_clk_o
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}
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C 5300 7500  1 0 0 out_port.sym
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{
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T 6300 7500 5  10 1 1 0 0 1 1
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refdes=aux_shift_dr_o
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}
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C 5300 7900  1 0 0 out_port.sym
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{
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T 6300 7900 5  10 1 1 0 0 1 1
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refdes=aux_select_o
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}
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C 5300 8300  1 0 0 out_port.sym
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{
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T 6300 8300 5  10 1 1 0 0 1 1
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refdes=aux_capture_dr_o
141 
}

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